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Bug report about function "HAL_HRTIM_UpdateEnable" and "HAL_HRTIM_UpdateDisable"

_exp
Visitor

‎2024-06-30 10:18 PM - edited ‎2024-07-01 01:41 AM

Hi, I'm developing my digitally controlled SMPS using stm32g474 MCU, I found that the arguments of the functions "HAL_HRTIM_UpdateEnable" and "HAL_HRTIM_UpdateDisable" may be wrong, and the code of the two functions  are copied as follow:

In stm32g4xxhal_hrtim.c

 

 

 

/**
  * @brief  Enable the transfer from preload to active registers for one
  *         or several timing units (including master timer).
  *   hhrtim pointer to HAL HRTIM handle
  *   Timers Timer(s) concerned by the register preload enabling command
  *                   This parameter can be any combination of the following values:
  *                   @arg HRTIM_TIMERUPDATE_MASTER
  *                   @arg HRTIM_TIMERUPDATE_A
  *                   @arg HRTIM_TIMERUPDATE_B
  *                   @arg HRTIM_TIMERUPDATE_C
  *                   @arg HRTIM_TIMERUPDATE_D
  *                   @arg HRTIM_TIMERUPDATE_E
  *                   @arg HRTIM_TIMERUPDATE_E
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
                                          uint32_t Timers)
{
   /* Check the parameters */
  assert_param(IS_HRTIM_TIMERUPDATE(Timers));

  /* Process Locked */
  __HAL_LOCK(hhrtim);

  hhrtim->State = HAL_HRTIM_STATE_BUSY;

  /* Enable timer(s) registers update */
  hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);

  hhrtim->State = HAL_HRTIM_STATE_READY;

  /* Process Unlocked */
  __HAL_UNLOCK(hhrtim);

  return HAL_OK;
  }

/**
  * @brief  Disable the transfer from preload to active registers for one
  *         or several timing units (including master timer).
  *   hhrtim pointer to HAL HRTIM handle
  *   Timers Timer(s) concerned by the register preload disabling command
  *                   This parameter can be any combination of the following values:
  *                   @arg HRTIM_TIMERUPDATE_MASTER
  *                   @arg HRTIM_TIMERUPDATE_A
  *                   @arg HRTIM_TIMERUPDATE_B
  *                   @arg HRTIM_TIMERUPDATE_C
  *                   @arg HRTIM_TIMERUPDATE_D
  *                   @arg HRTIM_TIMERUPDATE_E
  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
                                          uint32_t Timers)
{
  /* Check the parameters */
  assert_param(IS_HRTIM_TIMERUPDATE(Timers));

  /* Process Locked */
  __HAL_LOCK(hhrtim);

  hhrtim->State = HAL_HRTIM_STATE_BUSY;

  /* Enable timer(s) registers update */
  hhrtim->Instance->sCommonRegs.CR1 |= (Timers);

  hhrtim->State = HAL_HRTIM_STATE_READY;

  /* Process Unlocked */
  __HAL_UNLOCK(hhrtim);

  return HAL_OK;
  }

 

 

 

 The purpose of two functions should be disable or enable the transfer from preload to active registers, however the second argument of the function is the software update register shown below, not the transfer disabling register. 

In stm32g4xxhal_hrtim.c

 

 

 

/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
  * @{
  * @brief Constants used to force timer registers update
  */
#define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */
#define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */
#define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */
#define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */
#define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */
#define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */
#define HRTIM_TIMERUPDATE_F         (HRTIM_CR2_TFSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer F */
/**
  * @}
  */

 

 

 

In stm32g474xx.h

 

 

 

/**** Bit definition for Common HRTIM Timer control register 2 ****************/
#define HRTIM_CR2_MSWU_Pos            (0U)
#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)           /*!< 0x00000001 */
#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                      /*!< Master software update */
#define HRTIM_CR2_TASWU_Pos           (1U)
#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)          /*!< 0x00000002 */
#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                     /*!< Timer A software update */
#define HRTIM_CR2_TBSWU_Pos           (2U)
#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)          /*!< 0x00000004 */
#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                     /*!< Timer B software update */
#define HRTIM_CR2_TCSWU_Pos           (3U)
#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)          /*!< 0x00000008 */
#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                     /*!< Timer C software update */
#define HRTIM_CR2_TDSWU_Pos           (4U)
#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)          /*!< 0x00000010 */
#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                     /*!< Timer D software update */
#define HRTIM_CR2_TESWU_Pos           (5U)
#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)          /*!< 0x00000020 */
#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                     /*!< Timer E software update */
#define HRTIM_CR2_TFSWU_Pos           (6U)
#define HRTIM_CR2_TFSWU_Msk           (0x1UL << HRTIM_CR2_TFSWU_Pos)          /*!< 0x00000040 */
#define HRTIM_CR2_TFSWU               HRTIM_CR2_TFSWU_Msk                     /*!< Timer F software update */

 

 

 

With current code in the HAL driver, the "HAL_HRTIM_UpdateDisable" function actually have the same effect as function "HAL_HRTIM_SoftwareUpdate" as shown below, and the "HAL_HRTIM_UpdateEnable" function have no effect to the HRTIM.

In stm32g4xxhal_hrtim.c

 

 

 

/**
  * @brief  Trig the update of the registers of one or several timers
  *   hhrtim pointer to HAL HRTIM handle
  *   Timers timers concerned with the software register update
  *                   This parameter can be any combination of the following values:
  *                   @arg HRTIM_TIMERUPDATE_MASTER
  *                   @arg HRTIM_TIMERUPDATE_A
  *                   @arg HRTIM_TIMERUPDATE_B
  *                   @arg HRTIM_TIMERUPDATE_C
  *                   @arg HRTIM_TIMERUPDATE_D
  *                   @arg HRTIM_TIMERUPDATE_E
  *                   @arg HRTIM_TIMERUPDATE_F
  * @retval HAL status
  * @note The 'software update' bits in the HRTIM control register 2 register are
  *       automatically reset by hardware
  */
HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
                                           uint32_t Timers)
{
  /* Check parameters */
  assert_param(IS_HRTIM_TIMERUPDATE(Timers));

  if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Process Locked */
  __HAL_LOCK(hhrtim);

  hhrtim->State = HAL_HRTIM_STATE_BUSY;

  /* Force timer(s) registers update */
  hhrtim->Instance->sCommonRegs.CR2 |= Timers;

  hhrtim->State = HAL_HRTIM_STATE_READY;

  /* Process Unlocked */
  __HAL_UNLOCK(hhrtim);

  return HAL_OK;
}

 

 

 

For realizing the wanted disable or enable the transfer from preload to active registers effect to the HRTIM, the accessed registers should be MUDIS, TAUDIS ... , shown below :

In stm32g474xx.h

 

 

 

/**** Bit definition for Common HRTIM Timer control register 1 ****************/
#define HRTIM_CR1_MUDIS_Pos           (0U)
#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)          /*!< 0x00000001 */
#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                     /*!< Master update disable*/
#define HRTIM_CR1_TAUDIS_Pos          (1U)
#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)         /*!< 0x00000002 */
#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                    /*!< Timer A update disable*/
#define HRTIM_CR1_TBUDIS_Pos          (2U)
#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)         /*!< 0x00000004 */
#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                    /*!< Timer B update disable*/
#define HRTIM_CR1_TCUDIS_Pos          (3U)
#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)         /*!< 0x00000008 */
#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                    /*!< Timer C update disable*/
#define HRTIM_CR1_TDUDIS_Pos          (4U)
#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)         /*!< 0x00000010 */
#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                    /*!< Timer D update disable*/
#define HRTIM_CR1_TEUDIS_Pos          (5U)
#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)         /*!< 0x00000020 */
#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                    /*!< Timer E update disable*/
#define HRTIM_CR1_TFUDIS_Pos          (6U)
#define HRTIM_CR1_TFUDIS_Msk          (0x1UL << HRTIM_CR1_TFUDIS_Pos)         /*!< 0x00000040 */
#define HRTIM_CR1_TFUDIS              HRTIM_CR1_TFUDIS_Msk                    /*!< Timer F update disable*/

 

-------

I found that the "HAL_HRTIM_UpdateEnable" and "HAL_HRTIM_UpdateDisable" operates on CR1 registers and "HAL_HRTIM_SoftwareUpdate" operates on CR2 registers the software update register MSWU,TASWU, ... and the transfer disabling registers MUDIS, TAUDIS ... are in the same position in the CR1/CR2 register so the "HAL_HRTIM_UpdateEnable" and "HAL_HRTIM_UpdateDisable" functions can realize their original purpose.

 

 

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