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Adc using DMA for sine wave

GHARI.1
Associate II

‎2021-09-25 12:45 AM

Hi,

​

Iam using DMA technique to digitise a sine wave using nucleo-H743ZI2, where Adc clock frequency is 36.5MHZ . Iam taking single data at a time and sending out using usart with a baud rate of 250000, the issue I am facing is when I increase the input signal frequency I am unable to reconstruct the signal back what might be the issue can anyone help me out.

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12 REPLIES 12
Piranha
Chief II

‎2021-09-25 05:22 AM

Duplicate: https://community.st.com/s/question/0D53W000015baukSAA/adc-using-dma-i-am-modelling-the-issue-i-am-facing-is-i-am-unable-to-digitize-as-input-signal-frequency-is-increasing-can-anyone-help-me-out

Except for very low sample rates, capturing and sending single samples is not practical. What is the sample rate and DMA buffer size? Still not enough useful description of the problem. And learn splitting your thoughts into sentences...

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GHARI.1
Associate II

‎2021-09-25 05:47 AM

So, according to ADC clock frequency = 36.5 MHz and Tsampling = 1.5 ADC_Clock_cycles the sampling rate would be 3.65Msamples/sec. I am using DMA to store a single value and output that value when conversion complete trigger is raised in continuous conversion mode using Fast channel ADC.

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GHARI.1
Associate II

‎2021-09-25 05:51 AM

You are saying that for very low sample rates, capturing and sending single samples is not practical then how to see the output data.

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GHARI.1
Associate II
In response to Piranha

‎2021-09-25 05:52 AM

So, according to ADC clock frequency = 36.5 MHz and Tsampling = 1.5 ADC_Clock_cycles the sampling rate would be 3.65Msamples/sec. I am using DMA to store a single value and output that value when conversion complete trigger is raised in continuous conversion mode using Fast channel ADC.You are saying that for very low sample rates, capturing and sending single samples is not practical then how to see the output data.

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MM..1
Chief II

‎2021-09-25 11:41 AM

Sorry @GHARI.1​ , but your info and math is ... You dont define how bit width ADC you use, too your calculation 3,65Msamples is big *****.

Example you use 8bit ADC then have 3,65MBytes-s and say transfer it over baudrate 250000 , that is simple 27kBytes-s

As you can see your teory is fail.

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GHARI.1
Associate II
In response to MM..1

‎2021-09-25 07:11 PM

Hi @MM..1​ the number of bits for ADC is 16 bits. As you said the baud rate and sampling rate are not matching but how to collect the adc data with high sampling rate.​

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MM..1
Chief II
In response to GHARI.1

‎2021-09-26 03:45 AM

ADC clock frequency not define sample rate. ADC clock define only speed for one sample and this speed too defines bandwith , here is critical out impedance of source measured signal. Formulas is in datasheets or AD theory.

I recommend as first understand this. Then choice system to transfer samples to ??? I mean UART to PC? USW.

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GHARI.1
Associate II
In response to GHARI.1

‎2021-09-26 04:10 AM

I am choosing T sampling as 1.5 clock cycles and in the data sheet they are mentioning Tconversion is 8.5 cycles for 16 bit so total time for 1 sample is 10 clock cycles that gives rise to 3.65 Msamples/sec if adc clock is 36.5MHZ. How to collect this adc data​

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MM..1
Chief II
In response to GHARI.1

‎2021-09-26 04:14 AM

Collect to ??? when PC then USB HS is best channel ...

Or i explain you what you do now:

  1. ADC collect samples
  2. USART read one and send on speed around 28kB you send 16bit one sample then result speek is 14kS
  3. you skip big amount ADC collected samples (250) and read next
  4. result is max transfered singnal is 14/2 = 7kHz max
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