ADC sample rate impossible to set precisely (calculations added)

[Robmar]

I realise that with ADC timer triggered DMA of 32 samples, you can set the timer precisely, but not the ADC​ per sample clock, so the samples get bunched up or stretched in the frame. The number of clocks per sample is limited, adjusting the APB2 clock hardly helps. A bit more flexibility on sample clocks would be really useful, I guess there is no easy solution?

Objective: capture ADC samples spread evenly at 96 KS/s on STM32F407VG with 8MHz xtal

Reference: STM32F406VG datasheet.

Overview:-

To capture samples from two independent ADCs at 96 KS/s, Timer3 is set to generate

an event every 1/3 mS, i.e. 333.3r uS

ABP1 Clk 84 MHz drives Timer3 from a 42MHz clk via a fixed x2 multiplier.

ADC-DMA is triggered and set to take 32 samples:

APB2 (PCLK2 + prescaler /4,/6,/8) clk drives ADCs at 84 MHz: Period 11.904 nS

Okay, so 3,000 triggers of 32 samples pers second.

1. 3K triggers the ADC-DMA every 333.3r uS

2. 32 samples every 333.3r uS gives 10.416r uS per ADC sample.

3. a1) ADC clk at 84 MHz has a clk period of 11.904761 nS or 0.011904761 uS,

  b1) Prescaler of 8 reduces this to 10.5 MHZ, and a clk period of 0.095238088 uS

  c1) Prescaler 6 clk reduces to 14 MHz and a clk of 0.07142857 uS. 

  d1) Prescaler 4 clk reduces to 21 MHz and a clk of 0.04761904 uS. 

  e1) Prescaler 2 (MX deselected not peritted) clk ... 42MHz ...

  b1-R) P8: We need 10.416 uS worth of clocks per sample, giving 109.375008312501 clks at 10.5 MHz

  c1-R) P6: -""-, giving 145.82400291648 clks at 14 MHz

  d1-R) P4: -""-, giving 218.736034997776 clks at 21 MHz

  e1-R) P2: -""-, giving 437.472 clks at 42 MHz (MX deselected)

Each samples takes 15 clks + (3, 15, 28, 56, 84, 112, 144, 480 sample time clks selectable)

Best match: Prescaler 8, our 96KHz sampling rate requires 109.375 clks per 32 sample trigger, subtracting the ADC sample time of 15 for 16-bit conversion = 94.375 clks, nearest selection is Sample time of 84 + 15 = 99, an increase in sample rate by 10.375 clks per sample.

This increase in the sample rate will require a significant non-standard change to my DSP code. A single transfer per trigger would solve this if there was a way that the ADC-DMA could increment the memory address, but so far I can't see that is supported.

[Robmar]

Unless you are able to explain exactly where one selects this "single sample transfer with DMA to incremented memory" mode, what you´re saying has very little value.

Do you really know how?

[Robmar]

The application needs at the very least 96 KHz sample rate due the FFT requirements.

[Piranha]

> Unless you are able to explain exactly where one selects this "single sample transfer with DMA to incremented memory" mode, what you´re saying has very little value.

That is the only mode the DMA does, because there is no "transfer multiple non-existing samples" mode - you made that up in your fantasies!

Until you read the reference manual... "what you´re saying has very little value". Open it and read the section "13.8.1 Using the DMA":

When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each conversion of a regular channel, a DMA request is generated.

[Robmar]

So what?! I need it to increment the memory address ​each trigger, and reset the address after n samples.

Tell me where it says that's possible on single sample triggered ADC-DMA ​transfers?

Think about it​

[Piranha]

So you need a spectrum up to 48 kHz. OK, fine. Just take a note - if it is because of some audiophool "requirements" from forums, "listening experts" etc., then it most likely is wrong.

[Piranha]

> So what?!

About what? The quote literally tells when exactly the DMA request is generated! The DMA services the request and sits idle until the next one, not reads the same register multiple times with a maximum rate for no purpose. Incrementing (or not) memory address and setting a buffer length are DMA features and does not depend on ADC in any way.

> Think about it​

Think about reading the reference manual and all the posts in this topic! There is no special note in documentation like: "The only way, the DMA works, is actually possible."

Why don't you just try it? Set the timer triggering ADC with a 96 kHz rate and set the DMA to circular mode with 2*32 transfers. That's it!

[Robmar]

And the EOC per conversion, not end of conversions? Then it'll just have time to do one sample until the next trigger....mmm I hope, will test that out, fingers crossed​

[Robmar]

Question is this, once triggered, does the ADC​ start the next sample in sequence early if triggered before the next sample, or just ignore the triggers until it completes all samples?

Do I disable DMA continuous requests so that the trigger handles sampling?

This behaviour isn't clearly detailed as far as I have seen.​

[waclawek.jan]

There are no "DMA continuous requests". Please stop using the Cube/HAL lingo. Read RM. Use teriminology from there.

> Question is this, once triggered, does the ADC​ start the next sample in sequence early if triggered before the next sample, or just ignore the triggers until it completes all samples?

I don't know but that's entirely irrelevant. You want 96ksps, ADC is perfectly capable of completing a sampling+conversion cycle within 1/96kHz, if timing is set up properly.

> I need it to increment the memory address ​each trigger,

That's what DMA does for you if DMA_SxCR.MINC is set.

> and reset the address after n samples.

That's what DMA does for you if DMA_SxCR.CIRC is set.

Read the TIM, ADC and DMA chapters in RM.

JW

[Robmar]

Please try to be calm okay, and remember that while you know what you're trying to say, the other person may need a clearer explanation.

Are you saying this:

Adc dma copies n samples to memory as adc samples complete following the timer trigger, right?!

I​n my code case, we start this requesting 32 samples to a circular buffer, ok?

But, with DMA constant requests disabled​, the bits are setup such that the timer trigger starts not the sequential dma transfers of all 32 samples, but just one adc dma transfer, of one sample, per trigger, is that what you're saying?

​PS talking of lingo, I don't know what RM is, and googling STM RM lists nothing.