Also: AN5537 How to use ADC Oversampling techniques to improve signal-to-noise ratio on
STM32 MCUs
https://www.st.com/content/ccc/resource/technical/document/application_note/group2/5f/8e/fb/19/fc/1e/48/4c/DM00722433/files/DM00722433.pdf/jcr:content/translations/en.DM00722433.pdf
Hardware oversampling feature overview
Note: This section concerns the STM32L4 series and information could slightly differ for other products. The dedicated documentation should be consulted.
The hardware oversampling engine accumulates the results of ADC conversions. The accumulated output data can be right-shifted (and rounded) to provide selected bit-depth in relation to OSR. The output value is not updated every sampling period, but once N samples are accumulated, therefore, the output data rate is
decimated by a factor of OSR.
The result is the average of accumulated samples as follows:
Result = 1
M ×
0
N − 1
Conversion tn (11)
Where both N and M can be adjusted:
• N is the oversampling ratio. It is set with the OVFS[2:0] bits in the ADC_CFGR2 register. It can be a factor
between 2x and 256x.
• M is the division coefficient (right bit shift). It is set with the OVSS[3:0] bits in the ADC_CFGR2 register. It
can allow to right shift the sum up to 8 bits.
In the case of STM32L4 series, the oversampling engine begins summing N samples. The sum is then right
shifted by M bits. The engine keeps the 16 least significant bits after the shift, and rounds the result to the nearest value according to the bits removed by the shifting.
The final result is saved in the ADC_DR data register and because of the 16-bit truncation, it cannot be
represented on more than 16 bits.
How to operate the bit-depth obtained with oversampling
When N samples of X bits are accumulated, the result can be coded on up to X + (ln(N) / ln(2)) bits.
For example, if the oversampling ratio N is 256x and the samples accumulated are on 12 bits, the sum of N terms will be on 20 bits since ln(256) / ln(2) = 8 and 12 + 8 = 20.
Next, the right shifting, which is up to 8 bits has to be taken into account.
Finally, the bit-depth is given by X + (ln(N) / ln(2)) – M but is limited to 16 bits because of the truncation.
Note: The number of bits X for a sample depends on the product used and can be found in its datasheet.
The Accumulate and average stage can be thought of as a kind of digital filter (often called accumulate-and-
dump). The frequency response of such filter is equivalent to a first order Cascaded-integrator-comb (CIC1)
Hogenauer filter. The frequency response in case of sampling frequency 1 MHz and OSR = 10 can be seen in Figure 13. Frequency response of accumulate-and-dump filter.
