ADC Common Status Register

[jerry2]

Posted on June 12, 2015 at 21:59

The STM32F429 has three ADCs: ADC1, ADC2, and ADC3. They all have a status register, which has an EOC bit to indicate conversion complete.

There's also a common status register (ADC_CSR) shared by all three ADCs that contains copies of the status bits of all three ADCs.When I start an ADC conversion on ADC1, it completes, and I see the EOC bit set in ADC1_SR, but EOC1 does not get set in ADC_CSR.Since all three ADCs share a common interrupt, I'm using the common status register to determine which ADC caused the interrupt by checking which EOCx bit is set, but it's not working because the EOCx bits are not getting set when their corresponding EOC bit is set in the ADCx_SR registers.I checked the STM32F429 errata, but see no mention of this. Is there something I need to do to get the EOCx bits to accurately reflect the state of the EOC bits in ADCx_SR?

[waclawek.jan]

Posted on June 12, 2015 at 22:19

How do you read it, in a debugger?

What about the other bits, e.g. STRT? JW

[jerry2]

Posted on June 12, 2015 at 23:33I've read it using a debugger and also just by reading the register in my code. In both cases, STRT1 is set in ADC_CSR, but not EOC1.

[raptorhal2]

Posted on June 12, 2015 at 23:37

Are you using the ADCs in multi-ADC mode, or running them independently? I believe the CSR is active only in multi mode.

Cheers, Hal

[jerry2]

Posted on June 12, 2015 at 23:54

I'm running them independently.

I read the manual petty thoroughly and didn't see anything that implied that the ADC_CSR is valid only in one of the multi modes, but then again, the documentation isn't always clear or complete.

[raptorhal2]

Posted on June 13, 2015 at 02:08

Look at the Single ADC and Multi ADC block diagrams in the Reference Manual. The CSR shows up only in the Multi ADC diagram. And only the multi ADC description paragraphs mention it.

CSR register description words like ''This bit is a copy of the EOC bit in the ADC3_SR register.'' strongly suggest that I am wrong. If it is set only in multi-mode, this would be a good place to say so. If ST doesn't pop in here to clarify, send them a request for a definitive explanation. Cheers, Hal

[jerry2]

Posted on June 15, 2015 at 19:31

I can see that the EOCx bits may only be active in multi-mode, but the documentation does not say that anywhere, and the STRTx bits do get set in ADC_CSR even when not in multi-mode. 

[Tesla DeLorean]

Posted on June 15, 2015 at 19:55

If ST doesn't pop in here to clarify, send them a request for a definitive explanation.

I'll kick it to moderation.