2 bit RTC->DR problem for STM32F767 (corrected title)

RKosst · ‎2022-06-23

I am using STM32F767, unfortunately I have a problem with the DR register area in the RTC. Exactly the problem is with the 10th and 17th bits of this register. Setting "1" means that I am not able to change these bits to "0". Only resetting the BDCR helps. Interesting fact: In the case of automatic date change (i.e. from July 31 to August 1) bit 10 in the DT register is automatically reset. Where could the problem be?

RKosst · ‎2022-06-28

Thanks for the answer and suggestions.

Registers after reset,

RTC-> TR = 0x52

RTC-> DR = 0x2101

RTC-> CR = 0

RTC-> ISR = 0x27

RTC-> PRER = 0x7f00ff

RTC-> WUTR = 0xffff

RTC-> ALRMAR = 0

RTC-> ALRMBR = 0

RTC-> SSR = 0x20

Then I program the time and date:

by setting in advance

RTC-> CAP = 0xCA;

RTC-> CAP = 0x53;

and ISR

Date: 0x224628

Time: 0x193032

Immediately after sending the date and time to the register

RTC-> TR = (uint32_t) tmpTime;

RTC-> DR = (uint32_t) tmpreg;

and

RTC-> ISR & = (uint32_t) ~ RTC_ISR_INIT;

The registers are as follows:

RTC-> TR = 0x193032

RTC-> DR = 0x224628

RTC-> CR = 0

RTC-> ISR = 0x37

RTC-> PRER = 0x7f00ff

RTC-> WUTR = 0xffff

RTC-> ALRMAR = 0

RTC-> ALRMBR = 0

RTC-> SSR = 0

From now on, I will not present the bits I mentioned earlier (the rest can be changed)

Registers after trying to set the time to August 1, 2022:

(tmpreg = 0x222801

tmpTime = 0x194041)

RTC-> TR = 0x194041

RTC-> DR = 0x222c01

RTC-> CR = 0

RTC-> ISR = 0x37

RTC-> PRER = 0x7f00ff

RTC-> WUTR = 0xffff

RTC-> ALRMAR = 0

RTC-> ALRMBR = 0

RTC-> SSR = 0xfd

Vbat is stable

waclawek.jan · ‎2022-06-28

I see.

This all looks OK (except for the result).

Does the unexpected value in DR persist even after some time, when TR changes naturally from running RTC?

Can you please set RTC->CR.BYPSHAD=1, and then try to do the same?

How is the APB1 clock set? And how is RTC clocked?

JW

PS. RTC-> CAP? Do you mean RTC->WPR?

RKosst · ‎2022-06-29

As I wrote earlier, the DR value changes correctly by itself. The problem only affects the update and only 2 bits in the DR register. I don't know what is causing this and I don't understand the mechanism. I also don't know how to do it to set it up correctly. Unfortunately, as I wrote, from time to time, regardless of me, the time and date will be updated.

With RTC-> CR.BYPSHAD = 1 set, it behaves identically. The difference is that in debugging I can change the date in the DR register by "clicking the mouse" (unfortunately when I change bits -10 and 17 in RTC-> DR to "1", I am not able to change them back to 0). The RTC clock is clocked from a LSE 32768Hz oscillator.

APB1 - peripheral clocks: 54MHz; APB1 Timer clocks: 108MHz.

I did a quick support for Ethernet only, from where I download the time update and only the RTC. The behavior is identical.

RTC-> CAP? Do you mean RTC->WPR?

Yes, I was wrong. Sorry

I will also add that at the end of the function that sets the time and date registers, I put RTC-> WPR = 0xFF;

waclawek.jan · ‎2022-06-29

Hummm....

I am out of ideas at this point. I also don't have a 'F767 to try. You may want to contact ST directly, through FAE or through the web support form.

JW

PS. @Peter BENSCH , don't you happen to have a 'F767 to try to reproduce this?

Peter BENSCH · ‎2022-07-01

Unfortunately not, but I will try to get a board with STM32F767 and follow this up, but I ask for patience.

Regards

/Peter

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