2020-08-28 07:08 AM
ISSUE 1 :
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User option byte IWDG1_SW in register FLASH_OPTSR[4] not working correctly with uVision V5.28.0.0 (MDK-ARM Essential).
Problem description:
After settings the user option byte IWDG1_SW = 0, to indicate HW start of Independent Watchdog I cannot load the image anymore using Keil.
The erase and program sequence start and progresses unusually quickly to:
Erase Done.
Programming Done.
Followed by many lines of:
Contents mismatch at: 08000000H (Flash=00H Required=88H) !
Contents mismatch at: 08000001H (Flash=00H Required=24H) !
...
And then
Too many errors to display !
Flash Load finished at ...
NOTE: Sometimes the problem is a different complaint related to memory access.
This issue happens regardless of settings the IWDG1_SW = 0 in code or from ST link utility.
Only the ST link utility manage to reflash the unit in this state, but usually only after unit manual reset.
Setup:
ISSUE 2 :
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Keil::STM32H7xx_DFP V2.5.0 (2020-03-23) file stm32h7xx_hal_flash_ex.h incorrectly defines
#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */ AND
#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */
This does not match the reference manual which indicates IWDG1_SW bit in register FLASH_OPTSR to be in position 4 (0x10U). This is confirmed also by the mask FLASH_OPTSR_IWDG1_SW which has value 0x10U.
Furthermore, not sure why definition OB_WWDG_SW and macro IS_OB_WWDG_SOURCE is defined, because it is not an option to enable with option byte?
2020-08-31 07:10 AM
Hi @Ernest Lotter ,
I'll try to reproduce and check Issue 1, then will keep you informed.
Regarding Issue 2: please note that stm32h7xx_hal_flash_ex.h was updated. Now we define: OB_IWDG1_SW, OB_IWDG1_HW, OB_IWDG2_SW and OB_IWDG2_HW.
This was done because in STM32H7 dual-core devices we have 2 IWDGs.
However, it remains wrong to define OB_WWDG_SW and OB_WWDG_HW. A request is tracked internally to remove them.
-Amel
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