STM32H743 Flash bank swap leads to WWDG reset

[Amihayl1]

Hello,

I am trying to perform a flash bank swap from bank1 to bank2. Executing the following code:

	FLASH_OBProgramInitTypeDef OBInit;
 
	/* Unlock tha User Flash area */
	HAL_FLASH_Unlock();
 
	HAL_FLASH_OB_Unlock();
 
	/* Get the Dual boot configuration status */
	HAL_FLASHEx_OBGetConfig(&OBInit);
 
	/* Get FLASH_WRP_SECTORS write protection status */
	OBInit.Banks     = FLASH_BANK_1;
	HAL_FLASHEx_OBGetConfig(&OBInit);
 
	/* Check Swap Flash banks  status */
	if ((OBInit.USERConfig & OB_SWAP_BANK_ENABLE) == OB_SWAP_BANK_DISABLE) {
		/*Swap to bank2 */
		/*Set OB SWAP_BANK_OPT to swap Bank2*/
		OBInit.OptionType = OPTIONBYTE_USER;
		OBInit.USERType   = OB_USER_SWAP_BANK;
		OBInit.USERConfig = OB_SWAP_BANK_ENABLE;
		HAL_FLASHEx_OBProgram(&OBInit);
 
		/* Launch Option bytes loading */
		HAL_FLASH_OB_Launch();
		SCB_InvalidateICache();
                NVIC_SystemReset();
	} else {
		/* Swap to bank1 */
		/*Set OB SWAP_BANK_OPT to swap Bank1*/
		OBInit.OptionType = OPTIONBYTE_USER;
		OBInit.USERType = OB_USER_SWAP_BANK;
		OBInit.USERConfig = OB_SWAP_BANK_DISABLE;
		HAL_FLASHEx_OBProgram(&OBInit);
 
		/* Launch Option bytes loading */
		HAL_FLASH_OB_Launch();
		SCB_InvalidateICache();
                NVIC_SystemReset();
	}
 
	return 0;

During the code fragment execution HAL_FLASH_OB_Launch() is called and I get a reset. Reset reason is WWDG reset.

When I execute this in step by step mode it is successful as the WWDG debug option is enabled.

If I enable the WWDG ISR and execute the bank swap function the ISR handler is not called but the reset reason is still WWDG reset and flash bank swap is not successful.

I have modified the HAL_FLASH_OB_Launch() and FLASH_OB_WaitForLastOperation(50000) to get some timestamps in a no_init ram section and saw that after SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); I get a WWDG reset. The counter did not expire and ISR Handler was not called.

PS. Interrupts are not disabled.

Watchdog refresh was added on few extra steps (in wait conditions) and before function calls to guarantee that this is not an issue.

Micro:STM32H743XIH6 revision V.

[Pavel A.]

> SCB_InvalidateICache

Try to disable ICACHE before the whole switching procedure. Or execute from RAM.

[FBL]

Hi @Amihayl1​,

I suggest starting with the example provided here,

STM32CubeH7/Projects/NUCLEO-H743ZI/Examples/FLASH/FLASH_SwapBank at master · STMicroelectronics/STM32CubeH7 (github.com) 

[Amihayl1]

Hello @F.Belaid​,

I have read the example code and the main function matches ours function code. The configuration of the micro differs as this is not being executed on a Nucleo board but on a in-house one.

The odd part is that this issue reproduces on 1 board of more than 20 tested.

While debugging this on this specific board I have disabled the WWDG and the operation completes successfully.

When WDG is enabled it does not complete nevertheless that I am refreshing the WDG on every instruction and every active wait.

I have added timestamps on most instructions as mentioned before and this leads to the impression that after SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); micro halts. As all interrupts are disabled and time between this instruction and calling FLASH_OB_WaitForLastOperation() is between 320 and 350 ms.

Additionally I have measured that the 3.3V on this specific board are ~3.20V but it should be well in the tolerance. Is there any correlation between power supply and speed of flash ?

Kind Regards,

Aleks

[FBL]

Hello @Amihayl1​,  

How long does the WDG take to reset.

Make sure that the reset does not occur during OB programming

In fact, after refresh, WWDG will expire after timeout and generate reset if counter is not reloaded.

[Amihayl1]

As mentioned before the WDG is refreshed on every instruction.

I have added debug code to read the timer from the WDG registers.

It did not expire also.

The WDG timeout is configured at 320ms