SWR bit of ETH_DMAMR does not get reset by hardware

[Benedikt Schmidt]

I have to examples of a PCB with a H735. On one of them HAL_Init for ethernet fails due to the SWR bit of ETH_DMAMR not getting reset by hardware. On the other example of the PCB everything is working fine, running the exact same binary.

Usually this seems to indicate an issue with REF_CLK. Unfortunately, REF_CLK is fine in both cases. The reference manual does not got into really more detail about what else could be missing or incorrect. As the exact same binary is working on a different PCB I expect the internals to be configured correctly by software. Hence, I assume an external signal is incorrect or in an incorrect state?

Regards,

Benedikt Schmidt

[Imen.D]

Hello @Benedikt Schmidt​ ,

Maybe this is due to the external MII/RMII clock!

So, check the pin configuration and the clock signal.

Have a look also at the errata sheet, and check if you have the same conditions as described in the Ethernet section.

I recommend you following the How to create project for STM32H7 with Ethernet and LwIP stack working article, it will help you in the Ethernet configuration.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Imen

[Benedikt Schmidt · Accepted solution]

Hi Imen,

as I wrote, I already checked the external clock. At least according to a visual inspection with the oscilloscope it was fine.

In the meantime a colleague figured out that the Ethernet Phy had an incorrect level on its reset pin. I still do not know how this exactly influenced the H7 to not clear the SWR bit, but setting this reset pin to a correct level fixed the issue.

Regards,

Benedikt Schmidt

[mayank]

Hello Benedict,

We have the exact same problem, which PHY are you using? We have an external micrel PHY. 

[Benedikt Schmidt]

I think it was a LAN8720AI, but I am not totally sure anymore.

[LCE]

For now I'm only using the H723 Nucleo and the H735 Discovery, both with the LAN8742 PHY, which provides the 50 MHz ref clock for STM32 RMII.

Here's part of my startup code, no failures, ever... ;)

uint8_t EthBaseInit(void)
{
	uint32_t u32TickStart = 0;
	uint32_t u32TempReg = 0;

	/* ETH clock enable */
	__HAL_RCC_ETH1MAC_CLK_ENABLE();
	__HAL_RCC_ETH1TX_CLK_ENABLE();
	__HAL_RCC_ETH1RX_CLK_ENABLE();

	__HAL_RCC_SYSCFG_CLK_ENABLE();

	/* reset Ethernet MAC peripheral */
	DelayX(100);
	__HAL_RCC_ETH1MAC_FORCE_RESET();
	DelayX(100);
	__HAL_RCC_ETH1MAC_RELEASE_RESET();
	DelayX(100);

	/* GPIO init */
	EthGpioInit();

/* set RMII Mode*/
	SYSCFG->PMCR &= ~(uint32_t)SYSCFG_PMCR_EPIS_SEL;
	SYSCFG->PMCR |= (uint32_t)SYSCFG_PMCR_EPIS_SEL_2;
	/* ### IMPORTANT dummy read to sync SYSCFG with ETH */
	(void)SYSCFG->PMCR;

/* SoftWare Reset */
	/* set SWR bit: resets all MAC subsystem internal registers and logic
	 * 	NOTE: the SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
	 *			not available -> check external PHY or IO configuration
	 */

	ETH->DMAMR |= ETH_DMAMR_SWR;
	/* wait for software reset to reset... */
	u32TickStart = HAL_GetTick();
	while( ETH->DMAMR & ETH_DMAMR_SWR )
	{
		/* timeout ? */
		if( (HAL_GetTick() - u32TickStart ) > ETH_TIMEOUT_SWRESET_MS )
		{
			uart_printf("# ERR: ETH_DMAMR_SWR software reset TO\n\r");
			return HAL_TIMEOUT;
		}
	}
...

[Calmout]

Hi Benedikt,

I am currently having the same issue with custom board and eth phy. Since I am new with the concept I need your help. Can you please explain in more detail what is meant by "incorrect level on its reset pin". My ethernet phy LAN8742AI has "nRST" pin that deals with external reset. If it is the issue how can I detect the incorrect level of this pin? 

Thank you in advance.

[Benedikt Schmidt]

Incorrect level meant in our case that the RST pin was not pulled down correctly to ground, therefore the PHY did not reset. I recommend using a voltmeter or oscilloscope and measure the voltage of the nRST pin during the reset procedure.

In our case the issue was a faulty reset-circuitry.