2024-06-05 10:16 PM - last edited on 2024-06-06 04:03 AM by Tesla DeLorean
Hello community,
I wanted to know how can I check the compatibility of of QSPI NOR FLASH with micro-controller, what are the parameter that will affect selection.
Are Infineon chips supported by STM32H7 family especially S25FL128SAGNFM003.
Solved! Go to Solution.
2024-06-06 03:59 AM - edited 2024-06-06 04:17 AM
The Hardware supports the part.
The Software must suitably configure the part and walk it into the correct/desired mode of operation at both ends.
Timing, must meet those specified by the chip, and the performance of the traces / pin drivers.
Choice of commands, bit lengths / widths of the phases, sufficient "dummy" cycles for the part to prefetch a buffer/line of data, or a couple, so it can stream bytes at high speeds, independently of the speed to fetch from the array.
A 16MB (128Mb) device can be addressed via 24-byte (3-byte) address, large devices will need 4-bytes, that mode may either need to be selected, or different sub-set of commands used.
You will be expected to read the data sheets and manuals for both the memory IC, and the MCU, to fully understand the expectations on both ends.
To program content, tools like STM32 Cube Programmer, need an "External Loader" that is aware of your part choice, board clocks, and board wiring. Given the wide variety of pin combinations these need to be customized to circumstances.
The Erase is a bit complicated, as there's a mix of sector sizes at the front/back (4KB), rest (64KB)
Got some support for the 256Mb models, and could likely add support for the 128Mb ones. https://github.com/cturvey/stm32extldr/tree/main/h7_s25sl256
2024-06-06 03:46 AM
Hello @sarun ,
To check whether a device is supported by QUADSPI interfaces, it is recommended to refer to the device datasheet and to the RM0434 15 Quad-SPI interface (QUADSPI) section and check if the command format and order in the datasheet memory are in line with the QUADSPI frame format and order (Instruction, Address, Alternate, Dummy, Data).
Each command can include five phases: instruction, address, alternate byte, dummy, data. Any of these phases
can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
Also the AN4760 Application note section 8 Supported devices, can also help you check memory compatibility with the QUADSPI interface.
Thank you
Kaouthar
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2024-06-06 03:59 AM - edited 2024-06-06 04:17 AM
The Hardware supports the part.
The Software must suitably configure the part and walk it into the correct/desired mode of operation at both ends.
Timing, must meet those specified by the chip, and the performance of the traces / pin drivers.
Choice of commands, bit lengths / widths of the phases, sufficient "dummy" cycles for the part to prefetch a buffer/line of data, or a couple, so it can stream bytes at high speeds, independently of the speed to fetch from the array.
A 16MB (128Mb) device can be addressed via 24-byte (3-byte) address, large devices will need 4-bytes, that mode may either need to be selected, or different sub-set of commands used.
You will be expected to read the data sheets and manuals for both the memory IC, and the MCU, to fully understand the expectations on both ends.
To program content, tools like STM32 Cube Programmer, need an "External Loader" that is aware of your part choice, board clocks, and board wiring. Given the wide variety of pin combinations these need to be customized to circumstances.
The Erase is a bit complicated, as there's a mix of sector sizes at the front/back (4KB), rest (64KB)
Got some support for the 256Mb models, and could likely add support for the 128Mb ones. https://github.com/cturvey/stm32extldr/tree/main/h7_s25sl256
2024-06-07 12:20 AM
Thank you for your inputs now I have a clear picture, did digging through data sheet of the component i needed and the components mentioned in AN4760, other than the alternate byte phase everything looks fine. yes as @KDJEM.1 mentioned it can be configured to skip and it is mentioned in section 3.1.3 of the the AN4760.
Once again Thank you for your input @Tesla DeLorean and @KDJEM.1