2023-10-11 04:45 AM
Solved! Go to Solution.
2024-06-06 04:54 AM
Hello @waclawek.jan, @Denial1, @TDK,
This behavior is now noted in Readme files of all HAL TIM examples calling HAL_TIM_PWM_ConfigChannel() with the output channel configured in PWM1 mode:
TIM_6Steps,
TIM_Asymetric,
TIM_CascadeSynchro,
TIM_Combined,
TIM_ComplementarySignals,
TIM_Dithering,
TIM_DMA,
TIM_DMABurst,
TIM_ParallelSynchro,
TIM_PrescalerSelection,
TIM_PWMOutput.
The note is the following:
In this examples, the output channel is configured in PWM1 mode meaning that in up-counting mode, channel 1 is active as long as TIMx_CNT < TIMx_CCR1. As, in the function HAL_TIM_PWM_Start* function, the output channel is enabled prior enabling the timer's counter a timing difference might be observed on the first generated PWM. This difference corresponds to the delay - in term of number of CPU cycles - between the channel enable and the counter enable in the HAL_TIM_PWM_Start* function.
Thank you!
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