How can I resolve ST-Link "No device found on target" error?

[OLyke]

TL;DR What's the magic sauce for connecting to an STM32F7 with SWD on ST-Link?

Hello everyone. I am perplexed because I have been unable to program my custom board based on the STM32F765VGT6. (Hardware Eagle files + pdfs, Logic data captures, and some screenshots attached for reference)

When I try to program my board with ST-Link I get the error

"Error in initializing ST-Link device.

Reason: (4) No device found on target."

But I can't find a lot of information on what that means.

My problem seems very similar to the unresolved thread here:

https://community.st.com/s/question/0D50X00009XkXslSAF/stm32f103rbt6-error-no-device-found-on-target

As suggested in that thread I have confirmed that:

• Reset is pulled high
• Boot0 is pulled low
• VCC is stable at 3.3V and appears at all desired pins of the board (according to AN4661, https://www.st.com/content/ccc/resource/technical/document/application_note/b0/5c/ba/b2/cb/10/41/dd/DM00164549.pdf/files/DM00164549.pdf/jcr:content/translations/en.DM00164549.pdf)
• GND is connected to all the necessary pins
• VCAP 1/2 connected to 2.2uF capacitors

Additional hardware details:

I have 20 ohm resistors in series with SDCLK and SWDIO, and those two lines also have 10k pullups to 3.3V -- holdover from my previous working design.

I have a 24 MHz external crystal with 18 pF caps.

I am using a custom cable to wire between CN6 on the ST-Link and my Corte debug style connection. I'm pretty sure I have triple-checked this but here it is anyway:

CN6 PIn ---> Cortex Pin ---> STM32 Pin

1 (AIN_1) ---> 1 (3.3V) ---> ---- (Board VCC @ 3.3V)

2 (SWCLK) ---> 4 (SWDCLK) ---> PA14 (SWCLK)

3 (GND) ---> 3 (GND) ---> ---- (Boad GND)

4 (SWDIO) ---> 2 (SWDIO) ---> PA13 (SWDIO)

5 (NRST) ---> 10 (Reset) ---> NRST (Pin # 14 on my LQFP100 package)

6 (SWO) ---> Not connected ---> Not connected

I also tried to program with a bare-minimum approach on a new pcb - this time without pullups on SWD lines and without external oscillator - still no luck.

I am using Atollic TRUEStudio in conjunction with STM32CubeMX, as well as an ST-Link that came with an F7 Nucleo dev board. The ST-Link can communicate with the Nucleo without any trouble ( and yes, I did remember to take off the jumpers to enable CN6... but not until after having a false moment of happiness! )

As an additional note: One of the two test boards was fully populated and reflowed in my school's oven. The other had only crucial power supply and programming connections and the microcontroller itself and was hand-soldered an an attempt to avoid damage to the IC. In both cases I got the same error message.

I'm really excited to start programming my board but this problem has been kicking my ****. Can anyone offer some insightful clues? I've uploaded as much contextual data as I could including the schematic, and board layout (simplified) as well as logic analyzer captures for a few different test scenarios. Finally I uploaded a separate logic capture of how the connection process should look (from programming my Nucleo). You can download the free software to view the '.logicdata' files here: https://www.saleae.com/downloads/

Thanks in advance!

[Piranha · Accepted solution]

Hello!

The problem is because You haven't connected VDDA and VSSA pins. Look at a reference schematic on page 38 of AN4661 "Getting started with STM32F7 Series MCU hardware development" and read section 1.2 "Power supply scheme" on page 11:

"VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. The VDDA pin must be connected to two external decoupling capacitors (100 nF ceramic + 1 μF tantalum or ceramic)."

Consider connecting VREF+ to VDDA. And VBAT also should be connected one way or another:

"VBAT = 1.65 to 3.6 V: power supply for the RTC, the external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no external battery is used, it is recommended to connect this pin to VDD with a 100 nF external ceramic decoupling capacitor."

[Tesla DeLorean]

What the other guy says..

Note NRST being clamped low in your plot.

With out connecting debugger check voltages on NRST and VCAP.

Lack of VDDA will clamp reset, as it is thresholded by the POR circuit.

Not seeing 1.25V on VCAP suggest a power or orientation issue.​

[OLyke]

Thank you both! I will try with those changes soon and come back with the results.

[OLyke]

Thanks @Piranha​ - This totally solved the problem.

[OLyke]

@Community member​ Thanks for explaining why VDDA is required - now I won't make that mistake again.

[ESpra.1]

Would this apply to every single VDD and VSS pairing on the board (e.g. a cold solder joint on one VDD or VDDIO pin when all others are set up)? And if so, what other pins does this apply to? I'm running out of places to poke with a logic analyzer and multimeter

[Tesla DeLorean]

Not sure of the exact bond-out, but generally speaking you'd not want to rely on the part internals to be a conduction path.

The analogue supplies tend to be most critical as these power the POR, Reset and PLLs

[ESpra.1]

Small update, turns out my modeling software decided that the connection between VDDUSB and 3V3 was its own net not connected to anything, and so it's not being powered. I'll update if a jumper fixes the problem.

Update: It did not, but it looks like there's a loose connection to the VDDA and VREF+ pins, so basically exactly what this thread was about initially.