120Mhz emissions from SDIO pins

[PCudd]

We are getting massive ammounts of emissions from the D0 SDIO pin with 120mhz and resonant freqs. The pins for SDIO have been set to AF but nothing else has been setup register wise yet, the circuit was taken from the appnotes with the 3v3 pullups on D0,1,2,3,CMD

APB2 periph is 60mz

APB2 timer 120mhz

[PCudd]

Yes, SDIO has not been implemented yet.

[Ozone]

I am no PCB designer, just had to collaborate with them occasionally.

Normal SPI/SDIO lines contain at least terminating resistors, check e.g. available schematics.

Making the track longer or shorter will change the resonance frequency, and thus "shift" the problem to another point.

You might need to collaborate with the SW designer and the project management in this regard.

There are PCB design tool available that include a RF analysis (before even prototyping), though they tend to be not cheap ...

[Javier1]

Have you proved SDIO clock?

If SDIO is not being used maybe the noise comes from somewhere else, what value of pullup resistors are you using?

Did you proved the power supply rails?(specially 3v3)

[PCudd]

proved as in measured and scoped?

47k on the 3v3 pullups

[Javier1]

probed as putting the oscilloscope probes (sorry for the v)

47K should be ok