When installing some StellarStudio plugins http://*.srxstudio.org , you can meet the issue : sun.security.validator.ValidatorException: PKIX path building failed It is typical IT Issue :face_screaming_in_fear: in each corporate company. “"Path bui...
Dear all, We are thrilled to announce that as of today, March 1st, 2024, SR5E1 device support in StellarStudio is available to the mass market ! This means that any user can effortlessly download the official StellarStudio installation packag...
Hi,I have configured 5 CAN Rx messages using Dedicated Rx buffers. In between running, I am losing CAN Rx message reception. DRX flag in the IR register is not being set once the problem occurs, thereby missing the Rx messages.I need a power cycle or...
Posted on February 28, 2018 at 08:40My company is working exclusively with Linux, and we have interest in the SPC5 MCUs. But I couldn't find any toolchain for Linux. the SPC5-STUDIO is based on eclipse and claim to be an 'OpenSource Integrated Devel...
if you configure one CDTM.DTM right after one TOM and use it to generate TOM_OUT and TOM_OUT_N, what is the smallest dtz interval you have been able to achieve?if I set the DTM to be clocked with SYS_CLK (100MHz), still the dtz gap can't go anything ...
I am using SPC58EC. When I compile same code with GNU and GHS(Green Hills Software) I see different results.int main(void) { uint8_t mode; MC_ME.PCTL[15].R = (uint8_t)18; mode = (uint8_t)MC_ME.MCTL.B.TARGET_MODE; //SPCSetRunMode /* Clear...
Hello, I am using SPC58EC-Disp board. Core2 is already active and has timer interrupts. I need to set a timer interrupt in Core 0. I am trying use PIT0 and PIT0 configuration is done by Core2 so I think I only need to do PIT0 Channel settings. Two co...
Please help to advise whether encounter this kind of issue as per below picture for reference as both part no. are still active in STM website which different in memory size.
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SPC58EC has one Interrupt Controller which supports two processors. You can give different vector tables for each core. Let's say two cores are active and one external interrupt (ADC, Timer) happened, what will be the process after this? Which core w...
