STM32 MCUs Embedded software

 I am seeing behavior on an STM32G474 that I cannot explain and would appreciate if anyone has seen this before.SetupMCU: STM32G474 (Nucleo-G474RE) COMP6   Positive input: PB11 (COMP6_INP / ADC1_IN14) Negative input: DAC2_CH1 HRTIM Fault 3 source: Internal Fault (FLT_Int) from COMP6 Fault filter: Disabled Fault counter threshold: 0 Fault polarity: Active HighDAC ConfigurationDAC2_CH1 configured as:Normal mode Connected to on-chip peripherals only Output buffer disabledRuntime code updates DAC2 every 1 ms:HAL_DAC_SetValue(&hdac2,                 DAC_CHANNEL_1,                 DAC_ALIGN_12B_R,                 dac_value);Verification PerformedVerified COMP6 configuration registers. Verified DAC2 DOR register contains expected value. Verified HRTIM Fault3 is the only enabled fault source. Disabled ADC sampling on PB11 (no change). Verified fault polarity behavior. Verified comparator output on a GPIO pin.ObservationWhen monitoring the COMP6 output pin directly, the comparator switche

It’s mentioned in RM0456 rev7 that manual trim must be done for device variants except STM32U535/545; U575/U585 Rev.X: However in CubeMX 1.8.0 manual trim is only applied for these devices, which only applies to half of the family: /* This is only needed for some devices/rev. */ if (((dev_id == 0x482UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x481UL) && (rev_id == 0x2001UL)) || ((dev_id == 0x481UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x476UL) && (rev_id == 0x1000UL)))For example my Nucleo-U5A5ZJ-Q board has dev_id=0x0481 and rev_id=0x3001 so the manual trim is not applied.Which one is correct ?

I am trying to do OTA programming modifications using the DUAL bank feature of my STM32U575 IC with 1Mbyte of memory.I have successfully done this when the program starts in BANK 1 and I reflash BANK 2. I change the User Option byte to OB_SWAP_BANK_ENABLE and the board reboots and successfully runs from BANK 2.Now, on the next firmware update, programming BANK 1 when I am operating from BANK 2 the HAL_FLASH_Program command fails on the first byte.The erase code is attached and it is very similar to others I have found on GIT for other products. Does the U5 have an inherent defect? any help would be greatly appreciated.

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hello team, Another day, new same issue. :pensive_face:I have setup the DCMIPP PIPE 1 for the stm32n6570 DK, so that it dumps frames in address 0x34200000 which maps to SRAM3 begin address I have enabled bothe the memories SRAM3 and SRAM4 but with out software erase, I used the MX tool for project generation , I goal is to mimic the Continous Mode example provided by ST, I have read about the appilication notes getting started with DCMIPP and the afew sections of intrest form the RM for the deve board on the topic. I however face the challenge  as stated in the Post Title, there Is are no interrups being called yet I set up the global intterrups for both the Pixel pipe and the CSI interfacing, "Still as shown in in the generated files" and set the clocks for the DCMIPP is set to 300Mhz and the CSI interface I had to manualy try setting up the  input clock freq for the IMX335 module to 20Mz as the MX tool does not provide for its setting, but I have this code commented out as there was

Hello,I am working with the STM32N6570-DK board and the MB1854B camera module.I am using the ST-provided example code:https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/STM32N6570-DK/Applications/DCMIPP/DCMIPP_ContinuousMode This example works fine — I can display the live camera feed on the LCD.Now I want to enable the HDR (High Dynamic Range) feature of the MB1854B sensor.My questions are:Which part of the example code needs to be modified to enable HDR?Is there a register configuration to switch the sensor to HDR mode?Is there an ST-provided driver or initialization sequence for HDR mode example?I am looking for guidance or documentation on which registers to configure and where to modify the code so that the captured image is in HDR mode and displayed properly on the LCD.Thanks in advance!

I have a Nucleo-H753ZI board for testing purposes. I used CubeMX to configure SPI4 as a slave. You can see the configuration code below. SPI4_TX is assigned to DMA1 Stream 3, Medium priority, SPI4_RX is assigned to DMA1 Stream 0, medium priority.I have a SPI master attached to the SPI4 which works as intended, i checked that on the oscilloscope. The Master transmits 1 Byte, wait for 50µs, reads another 4 bytes and based on the content of that 4 bytes, continues to clock more bytes in or out. The clock frequency is 12,5 MHz and 680ns pause between each byte. In my testcode below, the globaldata[4] = 10; defines that 10 more bytes will be clocked by the master. So the entire frame will contain 15 bytes.I am now executing three different variations of code leading to surprising results. When calling HAL_SPI_Receive_DMA, the function HAL_SPI_RxCpltCallback is called as expected. When calling HAL_SPI_TransmitReceive_DMA, the function HAL_SPI_TxRxCpltCallback is called as expected. But when

7.3.4 FLASH read operations4. If the application reads … high-cycle data not previously written, a double ECC error is reported …When storing a variable amount of data to high-cycle flash, or dealing with setting up a new/blank MCU, the SW needs to check high-cycle flash which may be empty.I am looking for a good best-practice for how the flash is meant to be used. One option I am looking at disabled the ECC NMI (ironically) and checks if non-0xffs are present before clearing faults and re-enabling the NMI and reading the data.This only really works if it can be assumed the data is complete. It will still results in faults if data is not complete for some reason.Another option I can think of is handling the ECC NMIs and just allow normal reads, catch and clear ECC errors and report failure.Is there any solid recommendation on what to do? I can’t find any application note with examples.

The STM32G474RE support 3 FDCAN and that fit my design well.  When I checked the nucleo board, the firmware does not have any CAN example.  I searched the ST website, the user, programmer and reference manual do not have any information on the registers and their memory map information.  Although I found “STM32 FDCAN running at 8 Mb/s on Nucleo boards” helpful, it does not give me enough information of the FDCAN 2 & 3’s interrupt vector location, calls, setup and etc.  I need a example template to set up my FDCAN.  Where can I find that?

  When I was developing the stm32u575, I needed to set the threshold for the bor (power-on reset). I wanted the device to reset when the voltage was below a certain level. While configuring the bor threshold for the stm32u575, I followed the configuration process of the stm32f405, but it didn't work. The program got stuck at HAL_FLASH_OB_Unlock(). Why did this happen? What was the problem? FLASH_OBProgramInitTypeDef OBInit; HAL_FLASHEx_OBGetConfig(&OBInit); OBInit.USERType = OB_USER_BOR_LEV; OBInit.USERConfig = OB_BOR_LEVEL_1; HAL_FLASH_OB_Unlock(); HAL_FLASHEx_OBProgram(&OBInit); HAL_FLASH_OB_Launch(); HAL_FLASH_OB_Lock(); 

Hello ST team,I'm facing the issue with STM32N6 DCMI DMA configurations, I could see the data flowing down from the cmos & clocking at 50MHZ. I could spot the first 4 pixels data (2 words) on live watch window. the next word data is intermittent & getting into DMA error 0x41,The cube MX (6.17.0) unable to generate the DMA init functions appropriately for DCMI, however i’ve added the Config explicitly,  Any suggestions on the below configurations? /*** @brief DCMI Initialization Function* @param None* @retval None*/static void MX_DCMI_Init(void){/* USER CODE BEGIN DCMI_Init 0 *//* USER CODE END DCMI_Init 0 *//* USER CODE BEGIN DCMI_Init 1 *//* USER CODE END DCMI_Init 1 */hdcmi.Instance = DCMI;hdcmi.Init.SynchroMode = DCMI_SYNCHRO_HARDWARE;hdcmi.Init.PCKPolarity = DCMI_PCKPOLARITY_FALLING;hdcmi.Init.VSPolarity = DCMI_VSPOLARITY_LOW;hdcmi.Init.HSPolarity = DCMI_HSPOLARITY_LOW;hdcmi.Init.CaptureRate = DCMI_CR_ALL_FRAME;hdcmi.Init.ExtendedDataMode = DCMI_EXTEND_DATA_12B;hdcmi.Init.J

Dear  Team,I am currently working on an application based on the STM32H563ZITx microcontroller using the NUCLEO-H563ZI development board.The application is designed as a gateway that communicates with another controller through a UART interface. The same UART interface is also used to program the target controller with firmware updates.For the software implementation, I am using STM32CubeH5 v1.6.0 and have adopted the Nx_Iperf reference project for the NUCLEO-H563ZI board to develop a web-based user interface.The following functionalities have been successfully implemented and tested:Reading data from the target controller via UART Writing data to the target controller via UART Firmware download and programming through the same UART interfaceHowever, I am encountering an issue when transferring firmware (.bin) files. The system appears to accept only about 54 KB of data, after which the transmission stops. As a result, I am unable to transfer larger firmware images.My application requi

I’m using stm32f103 timer cc event to trigger adc injected conv. But I failed. I can trigger it with timer trgo. This means my adc configuration is correct. LL_TIM_InitTypeDef TIM_InitStruct = {0}; LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0}; LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1); TIM_InitStruct.Prescaler = 0; TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_CENTER_UP_DOWN; TIM_InitStruct.Autoreload = 2249; TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; TIM_InitStruct.RepetitionCounter = 0; LL_TIM_Init(TIM1, &TIM_InitStruct); LL_TIM_EnableARRPreload(TIM1); LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL); TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM2; TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_ENABLE; TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_ENABLE; TIM_OC_InitStruct.CompareValue = 0; TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;

Hello,Because there is no active handle in DMA list for DCMI DMA initialization (bug!?) I searching for the ways to enable and use DMA, I can't find examples for parallel mode except for CSI serial, if I switch to use DCMIPP in parallel mode then the cubeMX do not generate msp initialization code function HAL_DCMIPP_MspInit for DCMIPP interface (no pinout, RCC, IRQ...), and in DMA list DCMI_PSSI handle stays inactive,all my attempts to setup DCMI DMA do not work and DMA throws error 0x40, DCMI and camera working well, I getting hsync and vsync callbacks firing and counters show correct values, I tryed various settings but still cant start DMA transfer, there is my test and msp initialization code, please check: uint32 err0 = HAL_DCMI_Start_DMA(&hdcmi, DCMI_MODE_CONTINUOUS, (uint32)frame_buff_DCMI, 320 * 240 / 2); uint32 err1 = HAL_DCMI_GetError(&hdcmi); HAL_Delay(5000); uint32 err = HAL_DCMI_GetError(&hdcmi); printf("DCMI %u %u, %u %u %u, %u %u\n", hdcmi.St

Hello everyone,I am currently working on an STM32-based project and have encountered an issue with UART communication. The UART works correctly after startup, and data is transmitted and received as expected. However, after running for several minutes, the communication suddenly stops and no further data is received.I have checked the wiring, baud rate configuration, and power supply stability. I also monitored the application for hard faults but could not identify the root cause. The issue occurs consistently after prolonged operation.Development Environment:MCU: STM32 Series IDE: STM32CubeIDE Communication: UARTHas anyone experienced a similar issue or can suggest possible causes and troubleshooting steps? Any guidance would be greatly appreciated.Thank you.

Hi all! Thank you for taking time to assist me. I am attempting to make a composite USB Device on the NUCLEO-C562RE. I found the Middleware USBX examples and the core drivers exist in my toolchain at: STM32CubeC5/middleware/usbx However, I cannot seem to find the middleware configuration for USBX in STM32CubeMX2. My pack manager in the STM32CubeMX2 is set to this default value: "cube.packManager.cmsisPackRepositories": ["https://developer.st.com/st-pack-server/api/v1/pidx/STMicroelectronics.pidx"] Please let me know if I have missed anything or if you need further information from me to figure out the root issue. The examples, linked above, clearly auto generated the USBX files using the MX2 software, but I could not find the documentation that allowed me to generate those files. I would greatly appreciate it if someone could assist me with this.   EDIT: I saw this forum that says support isn't out until Q3. Does that mean I have to write the generated cod

Hello!I am working on a project using the STM32U375CGUx MCU, and I am trying to implement a Stereo Audio Acquisition system using two omnidirectional digital PDM MEMS microphones.Hardware Setup: Microphone L: L/R pin tied to GND (Rising Edge data output). Microphone R: L/R pin tied to VDD (Falling Edge data output). Both microphones share the same lines connected to the MCU: PB4 (ADF1_SDI0) for the clock and PB3 (ADF1_CCK0) for the data stream. The Issue:When configuring the peripheral through STM32CubeMX, I am unable to set up a true Stereo configuration. I can only make it work in Mono.Looking at the generated HAL initialization code, I am forced to choose either MDF_BITSTREAM0_FALLING or MDF_BITSTREAM0_RISING for the FilterBistream parameter. There is no option/macro to sample both edges (interleaved) simultaneously on the same filter instance:AdfHandle0.Instance = ADF1_Filter0;AdfHandle0.Init.CommonParam.ProcClockDivider = 6;AdfHandle0.Init.CommonParam.OutputClock.Activation =

Hello,I’m working with custom board STM32F767BITX, trying to interface Standalone USB Host MSC, with no Free RTOS.Tried different reference, below is one reference which I followed  As soon as connected USB, it shows connected but after that it loop between this two calls alternatively, USBH_LL_PortDisabled() and USBH_LL_PortEnabled() which disconnect USB and connect again and continue to do that.So I dont understand the root cause of this, what trigger this to behave like this?Please guide me to fix this issue. void SystemClock_Config(void){ RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; RCC

Hi everyone,I'm working on a project using **STM32H753ZIT6** (Cortex-M7 @ 480MHz) to drive an **Alientek ATK-MD0430** 4.3" TFTLCD with **NT35510** controller via **FMC 16-bit 8080 parallel bus**.**Symptom: Screen is completely dead — no backlight, no image, NT35510 ID read returns 0x0000 or 0xFFFF.**I've been debugging this for two weeks and would appreciate any guidance.---### Hardware Configuration| LCD Signal | STM32 Pin | FMC Function ||-----------|-----------|--------------|| CS | PD7 | FMC_NE1 (Bank1) || RS | PD13 | FMC_A18 || WR | PD5 | FMC_NWE || RD | PD4 | FMC_NOE || RST | PG9 | GPIO Output || BL | PA8 | TIM1_CH1 PWM || D0-D15 | Standard FMC data bus pins | FMC_D0~D15 |### System ClockHSE=25MHz → PLL1 /5×192/2 = 480MHz SYSCLKPLL2 /5×120/3 = 200MHz → FMC (HCLK=240MHz)VOS Scale 0### What I've Tried (all failed)1. Copied NT35510 init sequence from Alientek's official MiniSTM32H750 example2. Fixed CMD/DATA addresses: CMD=0x6007FFFE, DATA=0x60080000 (RS on A18)3. MPU configured for

Hello. I’m facing strange issue in my design with STM32U575RGT6, revision “U”.Finally I discovered what is going on, but I don’t have ideas how to fix this.I’m using electronic switch to power ON and OFF the device:VBATT is 4.2V Li-Ion battery.One half of BAV70 diode is controlled by manual SWITCH (to power ON), second one by IO pin from uC (to maintain ON, and to OFF).Problem is that my program often hangs up in this function (I added LED blinks inside): if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { while (1) { HAL_GPIO_WritePin(POWER_ON_GPIO_Port, POWER_ON_Pin, GPIO_PIN_SET); HAL_Delay(100); HAL_GPIO_WritePin(POWER_ON_GPIO_Port, POWER_ON_Pin, GPIO_PIN_RESET); HAL_Delay(1000); } Error_Handler(); }Voltage on VCAP pins is 0.9 V, and often freezes in this level. Rarely steps up to 1.2V and program normally continues.I finally discovered that is caused by slow rising of VDD voltage. This is from my electronic switch:I can bypass the

I read a couple of topics that discussed having to use the external xtal to drive the 48 Mhz as opposed to HSI48.  When I run cube mx, the clock mux is greyed out and I cannot change the clock source.Am I chasing the right issue here and if so, how do I ungrey the clock mux?My IOC file is attached. 

Hi all, we have developed a video capture application and are field-testing this right now. In order to optimize perceptual quality, we are tuning the quality parameters to find a good trade-off.I saw in the h263encapi.h some features mentioned that are interesting to our application but could not find out if the VENC hardware actually supports it, likeRegion of interest cyclic intra refresh  Video stabilization (although I fear that memory bandwidth is a limit here)I have read the Hantro Software Integration Guide in the github repository but that does not go into detail on what is available on the STM32N6.It seems that there has been an earlier discussion in this topic mentioning an Internal ticket number: 209269Could we have a feature map on what the IP block actually supports and the related software documentation?Thanks a lot Simon

Good morning everyone,I need to drive an external pump using DAC out pheriperal.I am working with an STM32H562ZI microcontroller and have followed the guide available at the following link: Getting started with DACBelow is my current configuration:/** * @brief DAC1 Initialization Function * @param None * @retval None */static void MX_DAC1_Init(void){ /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; if (HAL_DAC_Init(&hdac1) != HAL_OK) { Error_Handler(); } /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; sConfig.DAC_DMADoubleDataMode = DISABLE; sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; sConfig.DA

Hi,We are currently evaluating the possibility of booting an STM32N655X0-based custom board from an SD card and would appreciate some guidance before committing to this design.Current Setup MCU: STM32N655X0 Custom hardware Currently, the FSBL is downloaded directly into RAM during development. The FSBL then loads the application from external flash. We would like to migrate to SD card boot. Understanding from UM3234While reviewing UM3234 - How to Proceed with Boot ROM on STM32N6 MCUs, I found the following description (page 15):In data transfer mode, the Boot ROM searches for two FSBL images. It first looks for a GPT header at LBA1. If GPT is present, the Boot ROM uses the GPT table to locate the FSBL images. If GPT is not found, it falls back to the default locations: FSBL1: LBA 128 FSBL2: LBA 640 Our goal is to use a single SD card for both: Storing the FSBL used by Boot ROM Storing application data using FileX What We TriedOption 1: GPT PartitioningWe partitioned the SD

I need to create, read and modify files using filex. Such files have names that uses cyrillic characters set (they must be codified using unicode 16 bit). It is possible to manage such files? Thanks