[STM32U575][GPDMA] Linked-list node fetch fails when a 36-byte node crosses 64KB SRAM1 boundaries (0x20010000, 0x20020000)
Hello:
Observation (empirical, multiple boundaries confirmed):
When placing DMA linked list nodes (36 bytes each = 9 words) sequentially in SRAM1,
if a single node spans certain addresses, the GPDMA channel enters DTEF state
when fetching that node.
Confirmed problematic boundaries in SRAM1 (192KB, 0x20000000 - 0x2002FFFF):
- 0x20010000 : crossing FAILS
- 0x20020000 : crossing FAILS
Both boundaries appear at 64KB intervals within SRAM1, which suggests
that SRAM1 may be internally organized as multiple 64KB blocks/banks.
Test cases:
Test 1: Node array starting at 0x20011A54 (natural placement)
- Nodes 1-1633: within bank containing 0x20010000-0x2001FFFF → OK
- Node 1634: spans 0x2001FFF8 - 0x2002001C → FAILS (crosses 0x20020000)
Test 2: Node array starting at (0x20010000 - 44)
- The first node spans 0x2000FFD4 - 0x2000FFF8 (OK)
- The second node spans 0x2000FFF8 - 0x2001001C → FAILS (crosses 0x20010000)
Test 3: Node array starting at (0x20010000 - 36)
- The first node ends exactly at 0x20010000
- No node crosses the boundary → OK
Root cause (inferred):
GPDMA appears to fetch each 36-byte linked list node as a single burst,
and this burst cannot cross what appears to be a 64KB internal SRAM1
boundary.
Workaround:
Place the entire linked list node array within a single 64KB region
by using explicit address placement:
static DMA_NodeTypeDef g_dmaNodes[N] @ 0x20010000;
Questions to STMicro:
1. Is SRAM1 internally organized as multiple 64KB banks/blocks?
2. Is this crossing limitation of GPDMA documented anywhere?
3. Should HAL_DMAEx_List_BuildNode validate node placement?
4. Are there other similar boundaries elsewhere (SRAM2, SRAM3)?
5. If this behavior is not currently documented in ES0499, could it be considered for inclusion in a future revision of the errata sheet?
I have checked ES0499 (latest revision available on st.com as of July 2026) and could not find any documented entry describing this behavior. I have also reviewed related community threads (e.g., #141509 'GPDMA with linked list for big buffers') which mention the 64KB limitation but do not specifically address linked-list node fetch crossing internal SRAM1 boundaries.