Technical Inquiry about STM32L4 ADC Configuration Issue

[xiaoyao]

Dear STM32 Technical Team:

Our original design is implemented on the STM32F407, utilizing a single ADC pin for analog signal acquisition. Upon detection of a key trigger signal, high-speed data acquisition is performed via TIM1-triggered ADC1 with DMA transmission, where Analog Watchdog 1 is configured with Threshold A for boundary supervision. In the idle state without a key trigger, TIM2-triggered ADC2 operates in background mode with Analog Watchdog 2 (Threshold B) to continuously monitor abnormal signal fluctuations in real time.

Due to the limited on-chip RAM of the STM32F407, we have migrated the firmware to the STM32L4S5 microcontroller. However, this device only features a single ADC peripheral, which prevents the independent dual-ADC operation implemented in the original design. Furthermore, although the STM32L4S5 integrates three analog watchdogs, the hardware does not support configuration of independent threshold levels for separate operational modes.

We kindly request your official technical recommendations and feasible implementation methods to realize the above two functions on the STM32L4S5, including triggered DMA-based ADC acquisition and background abnormal signal monitoring with two independent watchdog thresholds.

（Under the following configuration, Analog Watchdog 1 can be triggered normally, whereas Analog Watchdog 2 cannot.
Nevertheless, when the two watchdog modules are set with identical threshold values, both Analog Watchdog 1 and Analog Watchdog 2 are able to trigger.）

Best wishes,

Thanks.

 

 

[db16122]

For STM32F407, there is one set of analog watchdog which are ADC_CR1 register control bits.But for STM32L4 series, there are 3 set of analog watchdog as below:

The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels(1) remain within a configured voltage range (window). It looks similar with STM32F407.

The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDxCH[18:0] (x=2,3). The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set. So if the transfer happen from STM32F407 to STM32L4, the setting may need to be modified.

Which modification has been done?

[xiaoyao]

Dear Technical Support,

Thank you so much for your instruction.

The STM32L4 series only integrates one ADC module. To implement the two original working modes migrated from STM32F407, we make use of the ADC regular group and injected group respectively.

Mode 1 (Regular ADC Group)

The implementation of regular-group ADC with analog watchdog1, DMA and timer2 trigger is identical to that on STM32F407, and it passes our current test normally.

Mode 2 (Injected ADC Group)

We adopt ADC with analog watchdog2, interrupt and timer3 trigger for injected group sampling following your guidance. This function works properly after debugging, we really appreciate your help.

Since these two modes need to be switched dynamically in runtime, we implement enable/disable operations as shown below:

Mode 1 Enable & Disable

Enable

SET_BIT (hadc1.Instance->CFGR, ADC_CFGR_AWD1EN);

SET_BIT(hadc1.Instance->IER, ADC_IER_AWD1IE); 

Disable

CLEAR_BIT (hadc1.Instance->CR1, ADC_CR1_AWDEN);

CLEAR_BIT(hadc1.Instance->IER, ADC_IER_AWD1IE);

 

Mode 2 Enable & Disable

Enable

SET_BIT (hadc1.Instance->AWD2CR, ADC_AWD2CR_AWD2CH);

SET_BIT(hadc1.Instance->IER, ADC_IER_AWD2IE);

Disable

CLEAR_BIT (hadc1.Instance->AWD2CR, ADC_AWD2CR_AWD2CH);

CLEAR_BIT(hadc1.Instance->IER, ADC_IER_AWD2IE);

The other mistake we made previously was the incorrect callback function for AWD2 interrupt. We originally used HAL_ADC_LevelOutOfWindowCallback(), while the correct interrupt callback should be HAL_ADCEx_LevelOutOfWindow2Callback().

Thanks for your patient technical support.

Best regards

[db16122]

Congratulation!