STM32 MCUs

Pls help with FIT rate value for below components:STM32N657X0H3Q    - MCU LSM6DSVTR          - IMU Sensor M24M01E-FMN6TP    - EEPROM ST4SI2M0004TPIFW    - eSIM

 I am seeing behavior on an STM32G474 that I cannot explain and would appreciate if anyone has seen this before.SetupMCU: STM32G474 (Nucleo-G474RE) COMP6   Positive input: PB11 (COMP6_INP / ADC1_IN14) Negative input: DAC2_CH1 HRTIM Fault 3 source: Internal Fault (FLT_Int) from COMP6 Fault filter: Disabled Fault counter threshold: 0 Fault polarity: Active HighDAC ConfigurationDAC2_CH1 configured as:Normal mode Connected to on-chip peripherals only Output buffer disabledRuntime code updates DAC2 every 1 ms:HAL_DAC_SetValue(&hdac2,                 DAC_CHANNEL_1,                 DAC_ALIGN_12B_R,                 dac_value);Verification PerformedVerified COMP6 configuration registers. Verified DAC2 DOR register contains expected value. Verified HRTIM Fault3 is the only enabled fault source. Disabled ADC sampling on PB11 (no change). Verified fault polarity behavior. Verified comparator output on a GPIO pin.ObservationWhen monitoring the COMP6 output pin directly, the comparator switche

It’s mentioned in RM0456 rev7 that manual trim must be done for device variants except STM32U535/545; U575/U585 Rev.X: However in CubeMX 1.8.0 manual trim is only applied for these devices, which only applies to half of the family: /* This is only needed for some devices/rev. */ if (((dev_id == 0x482UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x481UL) && (rev_id == 0x2001UL)) || ((dev_id == 0x481UL) && (rev_id == 0x3000UL)) || ((dev_id == 0x476UL) && (rev_id == 0x1000UL)))For example my Nucleo-U5A5ZJ-Q board has dev_id=0x0481 and rev_id=0x3001 so the manual trim is not applied.Which one is correct ?

For the SMPS mode of the STM32H563MIY3Q, the datasheet recommends an inductor with an RMS current (Irms) rating of 1.4 A. However, the actual core current is only 50 mA. Is it acceptable to select an inductor with a lower Irms rating, such as 500 mA?

Hi,what would be recommended way to override internal LDO which is used for VDD11/VCAP preparation? Because of thermal management, we prepared external LDO to lower internal MCU temperature. In H5 family, there was an BYPASS bit in PWR management. Maybe shall I change Vos to lower level to let higher level LDO win? Or would you have other way :) Thanks!JM

On a secured STM32H7Sx device (in CLOSED or LOCKED product state), what is the recommended way of passing volatile data to lower HDPL levels?According to the reference manual, the SBS_RSSCMDR register can be used to pass volatile data from HDPL 1, 2 or 3 to HDPL 0 (RSS), so that part of the answer is covered:Bits 15:0 RSSCMD[15:0]: RSS commandThe application can use this bitfield to pass on a command to the RSS, executed at thenext reset.But what if you want to pass volatile data from HDPL 2 or 3 to HDPL 1?(E.g., HDPL 2 wants to call into HDPL 1 so HDPL 2 first needs to write some volatile command somewhere, then execute a reset, then HDPL 0 (RSS) boots, then HDPL 1 boots and picks up the volatile command from somewhere.)SBS_RSSCMDR cannot be used because RSS will interpret this value as well, and RSS might clear this value at the moment it boots HDPL 1.

Hello,I would like to report a documentation issue in RM0511 Rev6, section 15.9 (LCSC register map, Table 38).The introductory text states:> "The green cells indicate the register is in the VDD12o power domain. This implies those registers are not reset on Deepstop exit."However, in Rev6 the color highlighting is missing from the table — it is not possible to identify which LCSC registers are in the VDD12o power domain. This information is critical for correct Deepstop/low-power mode implementation, as registers in the VDD12o domain retain their values across Deepstop while others do not. **References:**- RM0511 Rev6, section 15.9, Table 38- RM0511 Rev5, section 15.9, Table 39Thank you.

I'm investigating a suspected flash corruption/ECC issue on an STM32H743.A read from flash address 0x081F0000 consistently causes a fault. The problem is that I'm not fully confident that the fault status registers can be trusted after the event, so I'm looking for a diagnostic approach that does not rely entirely on the captured fault information.Known facts:Accessing 0x081F0000 triggers a fault. ECC_FA2R does not show a failing address. STM32H7 flash ECC is evaluated only when flash is read. ECC granularity is 32 bytes (256 bits).My main question is:If I suspect flash corruption or an ECC problem, but do not fully trust the contents of CFSR, HFSR, BFAR, SR2, or ECC_FA2R after the fault, what is the recommended way to diagnose the problem?Would you:Perform a controlled BusFault-protected flash scan in 32-byte steps? Use HAL_FLASHEx_ComputeCRC() over the suspect region? Dump the entire flash bank via SWD/JTAG and verify externally? Use some other method?Has anyone seen a corrupted flas

I am trying to do OTA programming modifications using the DUAL bank feature of my STM32U575 IC with 1Mbyte of memory.I have successfully done this when the program starts in BANK 1 and I reflash BANK 2. I change the User Option byte to OB_SWAP_BANK_ENABLE and the board reboots and successfully runs from BANK 2.Now, on the next firmware update, programming BANK 1 when I am operating from BANK 2 the HAL_FLASH_Program command fails on the first byte.The erase code is attached and it is very similar to others I have found on GIT for other products. Does the U5 have an inherent defect? any help would be greatly appreciated.

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hello team, Another day, new same issue. :pensive_face:I have setup the DCMIPP PIPE 1 for the stm32n6570 DK, so that it dumps frames in address 0x34200000 which maps to SRAM3 begin address I have enabled bothe the memories SRAM3 and SRAM4 but with out software erase, I used the MX tool for project generation , I goal is to mimic the Continous Mode example provided by ST, I have read about the appilication notes getting started with DCMIPP and the afew sections of intrest form the RM for the deve board on the topic. I however face the challenge  as stated in the Post Title, there Is are no interrups being called yet I set up the global intterrups for both the Pixel pipe and the CSI interfacing, "Still as shown in in the generated files" and set the clocks for the DCMIPP is set to 300Mhz and the CSI interface I had to manualy try setting up the  input clock freq for the IMX335 module to 20Mz as the MX tool does not provide for its setting, but I have this code commented out as there was

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic: For reference, we are used the external loader implementation for development board from the following link: https://controllerstech.com/w25q-flash-series-part-8-quadspi-external-loader/ We request your support in:Verifying if our schematic connections for the QSPI interface may be contributing to the issue.Identifying any possible hardware or configuration-related causes for the external loader failure.

Hello,I am working with the STM32N6570-DK board and the MB1854B camera module.I am using the ST-provided example code:https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/STM32N6570-DK/Applications/DCMIPP/DCMIPP_ContinuousMode This example works fine — I can display the live camera feed on the LCD.Now I want to enable the HDR (High Dynamic Range) feature of the MB1854B sensor.My questions are:Which part of the example code needs to be modified to enable HDR?Is there a register configuration to switch the sensor to HDR mode?Is there an ST-provided driver or initialization sequence for HDR mode example?I am looking for guidance or documentation on which registers to configure and where to modify the code so that the captured image is in HDR mode and displayed properly on the LCD.Thanks in advance!

Hi We are developing a board with the STM32U073CCT6 CPU. Would it be possible to use a crystal with the following characteristics for the LSE?32.768KHz Cl=6pF/ESR=50kRIn this case, what would be the recommended capacitor values?BRGilberto 

I have a Nucleo-H753ZI board for testing purposes. I used CubeMX to configure SPI4 as a slave. You can see the configuration code below. SPI4_TX is assigned to DMA1 Stream 3, Medium priority, SPI4_RX is assigned to DMA1 Stream 0, medium priority.I have a SPI master attached to the SPI4 which works as intended, i checked that on the oscilloscope. The Master transmits 1 Byte, wait for 50µs, reads another 4 bytes and based on the content of that 4 bytes, continues to clock more bytes in or out. The clock frequency is 12,5 MHz and 680ns pause between each byte. In my testcode below, the globaldata[4] = 10; defines that 10 more bytes will be clocked by the master. So the entire frame will contain 15 bytes.I am now executing three different variations of code leading to surprising results. When calling HAL_SPI_Receive_DMA, the function HAL_SPI_RxCpltCallback is called as expected. When calling HAL_SPI_TransmitReceive_DMA, the function HAL_SPI_TxRxCpltCallback is called as expected. But when

Hello, I am trying to connect to the STM32F072C8T6 microcontroller via USB in the STM32CubeProgrammer, however I am getting:"Device is under read out protection ! If you want to disable RDP please reconnect with Read Unprotect enabled"So, when I check the Read Unprotect (MCU) checkbox, I get:"Please Power off Power on your device."After turning the power off/on, I see the same messages. I cannot connect to the MCU via USB in the STM32CubeProgrammer.I have tried different versions of STM32CubeProgrammer:v2.16.0v2.15.0v.2.13.0v.2.10.0v.2.8.0Moreover I tried on second computer with Windows 11 and I have the same issue.I'm trying to connect my custom board, but I also checked another hardware board (BluePill ) with the same STM32F072C8T6 MCU and it doesn't work either.Interestingly, using the DFU-util v0.8 program I can connect to the MCU and successfully read/write memory:  

hifor stm32G4 series, if MCU option byte IWDG_SW equal TRUE, and the software start the IWDG by calling HAL_IWDG_Init(),when a system reset happen( for example, call HAL_NVIC_SystemReset() or IWDG reset), will IWDG stop counting before  next time initialization?  

Hi, I met a strange issue of ADC overrun during flash erase.The ADC is configured with circular DMA+TIM3 triggered at 1khz:static void ADC_Config(void) { /* Enable clock */ RCC->AHBENR |= RCC_AHBENR_DMA1EN; RCC->APBENR2 |= RCC_APBENR2_ADCEN; RCC->APBENR1 |= RCC_APBENR1_TIM3EN; /* ADC Init */ ADC1->CR |= ADC_CR_ADVREGEN; uint32_t tick = SysTick->VAL; /* Startup delay */ while ((tick - SysTick->VAL) < 960); /* Calibration */ ADC1->CR |= ADC_CR_ADCAL; while (ADC1->CR & ADC_CR_ADCAL); /* TIM3 trigger, DMA enable */ ADC1->CFGR1 = ADC_CFGR1_EXTEN_0 | 3 << ADC_CFGR1_EXTSEL_Pos | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN; /* Use 14MHz ADC clock */ ADC1->CFGR2 = ADC_CFGR2_CKMODE_0; /* Enable overrun interrupt */ ADC1->IER = ADC_IER_OVRIE; /* Long sampling time */ ADC1->SMPR = ADC_SMPR_SMP1_0 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_2; /* Vref and Tint enable */ ADC1->CHSELR = ADC_CHSELR_CHSEL

HiI'm looking for STM32 Nucleo boards or similar microcontroller boards that have embedded SIM (eSIM) capabilities. However, I haven't been able to find any boards that directly support eSIM integration. Are there any Nucleo boards that are compatible with eSIM modules like ST4SIM, and how can I identify or find them?Thanks and Regards@avbST 

Hi, according STM32H743 datasheet VDDLDO pin in BGA packages can be supplied independently from VDD pins. The problem is that on STM32H743VIH BGA package VDDLDO and VDD physically shorted in the package. Is the datasheet misleading or I’m missing  something?  

Good morning,I have found contradictory information regarding the bypass requirements of the SMPS integrated in the microcontroller.In particular, the datasheet, section 3.4.4, states that 60 µF are required, implemented as 4 × 15 µF.However, this information appears to contradict what is stated in AN5967 (Table 4)  and in the Nucleo reference design (MB1940-N657x0Q-C02).My question is:Are the 20 µF stated in AN5967 and used in the Nucleo board sufficient to ensure proper operation of the SMPS?Best regards,Federico Filosomi

I am using an STM32G030C8T6.I have 10 boards built from the same PCB design and BOM. All boards use the same firmware.8 boards work correctly, but 2 boards show abnormal ADC readings.ADC channels used: PA1 = ADC_IN1 PA5 = ADC_IN5 PA6 = ADC_IN6 PB0 = ADC_IN8 PB1 = ADC_IN9 PB2 = ADC_IN10 VREFINT ADC configuration: 12-bit resolution Continuous conversion enabled Scan conversion enabled DMA circular mode Sampling time = 160.5 cycles VREFINT included in the scan sequence Problem:On the failing boards, when the battery is connected, some ADC channels become 4095.Example:LOAD_I_ADC = 4095PV_A_ADC = 4095BAT_A_ADC = 4095VREFINT_ADC = 4095Other channels still show valid values.Measured VDDA: Battery disconnected: 3.32V Battery connected: 3.33V To isolate the issue, I created a separate test project using only the following: ADC_IN9 (PB1) VREFINT Results with battery disconnected:adcBuf[0] = 1415adcBuf[1] = 1518These values appear normal.I then created another test proje

7.3.4 FLASH read operations4. If the application reads … high-cycle data not previously written, a double ECC error is reported …When storing a variable amount of data to high-cycle flash, or dealing with setting up a new/blank MCU, the SW needs to check high-cycle flash which may be empty.I am looking for a good best-practice for how the flash is meant to be used. One option I am looking at disabled the ECC NMI (ironically) and checks if non-0xffs are present before clearing faults and re-enabling the NMI and reading the data.This only really works if it can be assumed the data is complete. It will still results in faults if data is not complete for some reason.Another option I can think of is handling the ECC NMIs and just allow normal reads, catch and clear ECC errors and report failure.Is there any solid recommendation on what to do? I can’t find any application note with examples.

The STM32G474RE support 3 FDCAN and that fit my design well.  When I checked the nucleo board, the firmware does not have any CAN example.  I searched the ST website, the user, programmer and reference manual do not have any information on the registers and their memory map information.  Although I found “STM32 FDCAN running at 8 Mb/s on Nucleo boards” helpful, it does not give me enough information of the FDCAN 2 & 3’s interrupt vector location, calls, setup and etc.  I need a example template to set up my FDCAN.  Where can I find that?

Hello Friends,I am looking for MCU. Kindly suggest. Below are the minimum requirementsNeed two SPI.  Need to read data of two sensors via SPI simultaneosly & continously. Need one UART  Need smallest possible foot print.  WLCSP12/TSSOP20/UFQFPN20 Do not want to use external cyrstal for clock. Want to use internal clock Robust for shock, vibration.  Pricing is no issue.Kindly suggest..