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Max Motus
Visitor II
July 13, 2026
Question

Ultra-low-power supply architecture for STM32L476 (STOP2) — single LDO vs. dual-rail (AON + switched buck)?

  • July 13, 2026
  • 0 replies
  • 16 views

Hi all,

disclaimer: I used AI to translate my question to english:

I'm designing the power supply for a solar-charged, battery-powered outdoor device (wildlife camera controller) built around an STM32L476VG. I'd appreciate a sanity check of the architecture and the regulator choices.

System:

  • Input: 2S Li-Ion (NP-F pack), 6.0–8.4 V, reverse protection via P-FET
  • MCU in STOP2 most of the time (target sleep budget: < 10 µA for the whole board)
  • Always-on: MCU, RTC (AB1805), I2C EEPROM, a µA-class wake-up receiver
  • Switched loads (active phases only, seconds to minutes): LoRa module (TX approx 120 mA), SD card (write bursts approx 100 mA), OLED, GPS
  • Separate 5 V rail (TPS62147, EN-gated) for a Raspberry Pi that wakes for uploads

Current design: one 3.3 V rail from an MCP1703A (2 µA IQ, 250 mA), all loads behind individual load switches (TPS22919 etc.).

Concern: worst-case concurrency (LoRa TX + SD write + MCU + OLED) sums to approx 250 mA -right at the LDO's limit, and (8.4 − 3.3 V) × 0.25 A approx 1.3 W in a SOT-223 is thermally not viable. Right now only firmware scheduling prevents this.

Planned change (next board rev): dual rail —

  • 3V3_AON: MCP1703A, feeding only µA loads (MCU, RTC, EEPROM, wake receiver)
  • 3V3_PERIPH: synchronous buck with EN from MCU, feeding LoRa/SD/OLED/GPS; candidates: TPS62177 (500 mA, 4.8 µA in sleep mode via SLEEP pin, 22 µA otherwise) or TPS629210 (1 A, 4 µA IQ without extra pin handling)

Questions:

  1. Is the dual-rail split the sensible approach here, or is there a cleaner single-regulator solution for 8.4 V in / 3.3 V out with approx 2 µA IQ and 300+ mA capability that I'm missing?
  2. TPS62177 vs. TPS629210 for the peripheral rail — any field experience regarding light-load behavior, PFM noise near a LoRa radio, or startup into the SD card's inrush?
  3. The LoRa module doubles as a wake source (CAD), so in one operating mode the peripheral rail must stay up during STOP2 (buck idling at 4-5 µA + radio sleep). Would you keep the radio on the buck rail and accept that, or move the radio to the AON LDO and accept 120 mA TX pulses through the LDO approx0.6 W peaks, low duty cycle)?
  4. Back-powering: with 3V3_PERIPH off, the MCU's UART/SPI/I2C lines must not phantom-feed the peripherals. I currently park the GPIOs (low/analog) before switching off, and use SN74LVC1G126 (Ioff) where buffering is needed. Are series resistors in every signal line to switched loads considered good practice, and what values do you use without hurting SPI at 8-16 MHz?
  5. Input protection: besides the reverse-polarity FET, I plan a TVS on the battery rail (SMBJ10A class) against connector/cable transients. Anything else you'd consider mandatory for an outdoor solar-charged device (load dump from the charge controller, ESD on the panel input)?

Thank you,

Max

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