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Associate
July 13, 2026
Solved

NUCLEO-H755ZI-Q Concurrent Capacity to handle multiple Threads

  • July 13, 2026
  • 3 replies
  • 70 views

Hi ST Support Team,

              I am Yashwanth Melwanki, Associated with Quest-Global as Technical Architect. 
              In one of designs [WIP], we are considering NUCLEO-H755ZI-Q and have connected below Peripherals placed on seperate board. connection is through MROPH headers CN11 and CN12. 
              All these peripherals will be active and set to run at max speed to the interfaces they are conencted to STM [I2C / SPI / USB / eMMS etc]
              I wish to know, What is capacibility of STM32 to run and interact with these peripharals engaged at max speed? 
              
              1. x1 USB FS to USB hub controller
              2. x1 I2c to 2 GPIO expanders (24 bit each - one as GPO and Anlother as GPI)
              3. x1 I2C to 1 GPIO expander, dedicated as 24Bit GPI
              4. x1 Ethernet
              5. x2 SPI: One for DAC (16bit, 16 Channel) interface and Another for ADC (16bit, 16 Channel) interface
              6. x1 QSPI
              7. x2 I2S; One as Inout and anne as Output
              8. x5 Timer outputs
              9. x1 UART
              10. x1 USART
              11. x1 CAN
              12. x1 SD card connection
              
Regards,
Yashwanth

 

Best answer by mƎALLEm
  1. All these peripherals [mentioned in previous email] are independently connected to dedicated ports [except I2C for GPIO expander]; In that case what stops to use them concurrently?

I didn’t check the GPIO vs alternate functions used concurrently. If you did the check from your side it’s ok.

 

  1. Do you any WCA [Worst Case App] reports?

To my knowledge: No.

 

  1. Have you tested NUCLEO-H755ZI-Q to max throttle, where all the peripherals are run at max speed and operations are intact? 

No. As I said, you need to asses that by yourself for your use case

 

  1. Do you anticipate any hic-ups in concurrency?

 

I don’t think so. STM32H7 is a high performance family with a scattered architecture with three bus matrices and flexible DMA allowing you to avoid access contentions. But again you need to assess the performance according to your application needs.

 

  1. If you have any test / validation reports for NUCLEO-H755ZI-Q, kindly share the same. [Thermal, reliability, long hours testing etc]

Please ask that question in STM32 MCUs Boards and hardware tool forum board. In the other hand ST boards are not intended to be used in the final product they are only used for evaluation purpose. Please read this post.

 

Also, we need you help in review the schematics of this design, which we will share in couple of days

You will need to post that request separately in STM32 MCUs Boards and hardware tool forum board.

 

Hope that helps.

3 replies

mƎALLEm
ST Technical Moderator
July 13, 2026

Hello ​@Yashwanth Melwanki and welcome to the ST community,

Not obvious to answer to that by Yes or No.

1- First, you need to check if you can use all these peripherals at the same time over the GPIOs as some alternate functions share the same IO.

2- Second you need to assess the performance of the product yourself according to your application requirements by running all these peripherals in parallel. 

My recommendation is to use use maximum CPU frequency, use DMA whenever possible, enable the cache (instruction and data).

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
Associate
July 13, 2026

​​​​​​Hello mƎALLEm, thank you for quick response. 

  1. All these peripherals [mentioned in previous email] are independently connected to dedicated ports [except I2C for GPIO expander]; In that case what stops to use them concurrently?
  2. Application is reference platform for automation. Intent is to enable all the peripherals [concurrently] and start capturing / sending the data through STM32
  1. Do you any WCA [Worst Case App] reports?
  1. Have you tested NUCLEO-H755ZI-Q to max throttle, where all the peripherals are run at max speed and operations are intact? 
  1. Do you anticipate any hic-ups in concurrency?
  1. If you have any test / validation reports for NUCLEO-H755ZI-Q, kindly share the same. [Thermal, reliability, long hours testing etc]

Also, we need you help in review the schematics of this design, which we will share in couple of days

 

mƎALLEm
mƎALLEmBest answer
ST Technical Moderator
July 13, 2026
  1. All these peripherals [mentioned in previous email] are independently connected to dedicated ports [except I2C for GPIO expander]; In that case what stops to use them concurrently?

I didn’t check the GPIO vs alternate functions used concurrently. If you did the check from your side it’s ok.

 

  1. Do you any WCA [Worst Case App] reports?

To my knowledge: No.

 

  1. Have you tested NUCLEO-H755ZI-Q to max throttle, where all the peripherals are run at max speed and operations are intact? 

No. As I said, you need to asses that by yourself for your use case

 

  1. Do you anticipate any hic-ups in concurrency?

 

I don’t think so. STM32H7 is a high performance family with a scattered architecture with three bus matrices and flexible DMA allowing you to avoid access contentions. But again you need to assess the performance according to your application needs.

 

  1. If you have any test / validation reports for NUCLEO-H755ZI-Q, kindly share the same. [Thermal, reliability, long hours testing etc]

Please ask that question in STM32 MCUs Boards and hardware tool forum board. In the other hand ST boards are not intended to be used in the final product they are only used for evaluation purpose. Please read this post.

 

Also, we need you help in review the schematics of this design, which we will share in couple of days

You will need to post that request separately in STM32 MCUs Boards and hardware tool forum board.

 

Hope that helps.

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.