STM32 MCUs

Hello, I am using an STM32L431 and found an interesting behavior with TIM1 PWM output while debugging. Test conditions: - MCU: STM32L431- TIM1 CH2 PWM output- Debugger: ST-LINK- Debug halt enabled- DBGMCU TIM1 freeze enabled (DBG_TIM1_STOP) Observed behavior: TIM2:When the debugger halts the CPU (breakpoint or single-step),the PWM output keeps its current output state as expected. TIM1:When the debugger halts the CPU and TIM1 freeze is enabled,the PWM output no longer behaves like TIM2. Additional observations: 1. MOE remains set (MOE = 1). 2. With OSSI = 0:   the output appears to become high-impedance (or disconnected). 3. With OSSI = 1 and OIS2 = 0:   the output becomes Low. 4. With OSSI = 1 and OIS2 = 1:   the output becomes High. 5. If DBG_TIM1_STOP is disabled:   PWM continues running during debug halt. These results make it appear that TIM1 enters an Idle/Off-State condition during debugger halt and the output level is determined by OSSI/OIS settings. Questions: 1. Is this expec

Hi ST Team,I’ve been using STM32G473VET3 for my product for the past 2 years.Right now I’m testing the code which I’ve freezed an year ago. But it enters uart error callback as soon as it calls HAL_UART_RECEIVE_IT function.(Overrun error continuously even after clearing it, Also no data is sending in that line).Hence I’ve generated new code in the cubemx also. In that also same problem arises whenever HAL_UART_RECEIVE_IT is called.IDE version : 1.18.1MX version : 6.14.0G4 package version : V1.3.0

Hi everyone,​I'm currently developing a MIDI controller/audio device for guitar VST plug-ins.​The project features a guitar audio input using the CS4272K IC connected to an STM32F446RET6. Additionally, the STM32 will operate in USB High Speed mode using Microchip's USB3300 PHY.​My main challenge at the moment is finding or designing the standalone minimum circuit (schematic) for these components to move forward with the project. Could anyone provide some guidance or share reference schematics for this setup?​Thanks in advance!

Hi everyone,I want to read data from an SPI slave using SPI3 while the MCU is in STOP2 mode.The communication protocol requires me to transmit a command before receiving the response.I configured LPBAM according to the following YouTube tutorial, and my CubeMX/LPBAM configuration is shown in the attached screenshots.My observations are:If I use only the “Transmit Data” node, everything works correctly. If I add a “Receive Data” node after the transmit node, the SPI transaction stops when it reaches the receive node. However, the “LPTIM1_CH1” output continues to generate trigger signals. If I replace them with a single “Transmit Receive Data” node, neither SPI nor LPTIM1_CH1 works.Could you please explain what might be causing this behavior? Is there any additional configuration required to use the “Transmit Receive Data” node in LPBAM with SPI3 in STOP2 mode?Thank you. 

Can ST please fix this minor interconnection line missing in the RCC clock tree figure in RM0394.JW

Heyho,working on a new project with a STM32G431, for now on a Nucleo-32 board.I have lots of things running (bare-metal, mostly no HAL), then I needed a timer with a higher resolution than the SysTick (running at 1 ms, looks valid).The only 32-bit timer is TIM2, so I set it up to simply count up, no interrupts, only with pre-scaler set to get 1 counter period of 10 us at a clock of 96 MHz. The code below is changed to a period of 1 ms, for simpler comparison to the 1 ms tick.Here’s the setup:/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *//* TIM2 * 32 bit timer * init function * 10 us timer -> NO interrupt */void TimComInit(void){ /* peripheral clock enable */ __IO uint32_t u32TmpReg; RCC->APB1ENR1 |= RCC_APB1ENR1_TIM2EN; u32TmpReg = ( RCC->APB1ENR1 & RCC_APB1ENR1_TIM2EN ); (void)u32TmpReg; TIM2->CR1 = 0; TIM2->CR2 = 0; TIM2->SMCR = 0; TIM2->CCER = 0; TIM2->CCMR1 = 0; TIM2->CCMR2 = 0; TIM2->CCMR3 = 0; TIM2->DIER =

0x0BF97000 (system bootloader base per AN2606): the jump appears to succeed (In Debug reaches the bootloader region), but execution then breaks at an address inside the bootloader ROM with no further progress and no USB enumeration. The hardware boot path works correctly. The problem is purely on the software-jump path.I created an empty project in sample you can download and test it. I also attached my option bytes (i think everything is default).MCU: STM32H573 (also tested h523)/** ****************************************************************************** * @file dfu_jump.c * @author Uğur Tümer * @brief See dfu_jump.h. Implements the magic-word + soft-reset path into * the STM32H523 system bootloader (USB DFU on PA11/PA12). ****************************************************************************** */ #include "dfu_jump.h" /** Magic word stored in TAMP_BKP0R between the request and the next boot. */ #define DFU_JUMP_MAGIC 0xDEADB007UL #define BOOT

I built a low-power board using an STM32L031. The code I use to enter STOP mode and STANDBY mode is shown below.In STANDBY mode, the board consumes about 2 µA. However, in STOP mode, it consumes about 90 µA, and I am not sure why there is such a large difference.The circuit only consists of the STM32L031 and the power supply section. Could there be a problem with my code? Why is the current consumption so much higher in STOP mode than in STANDBY mode? void EnterStopMode(void){ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_2); HAL_NVIC_ClearPendingIRQ(EXTI2_3_IRQn); HAL_SuspendTick(); HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); SystemClock_Config(); HAL_ResumeTick();}void EnterStandbyMode(void){ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB); HAL_PWR_EnterSTANDBYMode();}

Hi there,I am frustrated while searching the web for an normally easy task - 😒I am not able to detect, where Boot0 pin is on STLink-v3MODS module Rev.B.Does anyone know?I also asked ChatGPT and Google, but this only results in false answers - bricking the device.Please hlep - Thanks a lot.STLink-v3MODS Rev.B - front STLink-v3MODS Rev.B - backST32CubeProgrammer v.2.2.3.0 

Dear STM32 Community,I am using the STM32H745ZIT3 microcontroller with STM32CubeIDE for firmware development.I am facing an issue related to GPIO behavior during a watchdog reset.When a warm reset is triggered by either the Independent Watchdog (IWDG) or the Window Watchdog (WWDG), all GPIOs are reset to their default state. In my application, I need certain GPIO outputs (such as relay control signals) to retain their previous state during a watchdog reset, or at least avoid changing state until the application reinitializes them.Could you please clarify the following?Is it possible to prevent GPIOs from resetting during an IWDG or WWDG reset on the STM32H745ZIT3? Are there any software techniques to retain the GPIO output state across a watchdog reset? If GPIO retention is not supported, what is the recommended approach to prevent unwanted output glitches during a watchdog reset?Any guidance, application notes, or recommended design practices would be greatly appreciated.Thank you for

Post edited by ST moderator for the code. Hi,I have a pre-production batch of about 80 STM32L051 custom boards.Under certain circumstances, the microcontroller goes into sleep mode and waits for an IRQ to restart.Of these 80 boards, about 10 randomly, after going into sleep mode, don't restart (until a reset).This is the code I use:__HAL_GPIO_EXTI_CLEAR_IT( VIB_SENS_MAIN_Pin);__HAL_GPIO_EXTI_CLEAR_IT( VIB_SENS_BACKUP_Pin);NVIC_EnableIRQ( EXTI4_15_IRQn);HAL_COMP_Stop_IT( &hcomp1);HAL_COMP_Stop_IT( &hcomp2);__disable_irq();__HAL_PWR_CLEAR_FLAG( PWR_FLAG_WU);__HAL_GPIO_EXTI_CLEAR_IT( VIB_SENS_MAIN_Pin);__HAL_GPIO_EXTI_CLEAR_IT( VIB_SENS_BACKUP_Pin);__HAL_COMP_COMP1_EXTI_CLEAR_FLAG();__HAL_COMP_COMP2_EXTI_CLEAR_FLAG();delay_us( 5);HAL_SuspendTick();HAL_PWR_EnterSTOPMode( PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);HAL_NVIC_SystemReset();What did I do wrong?Thanks for the suggestion. 

Hello,I have programmed the OTP word 31 to 0xBBBBBBBB as follows, but when I want to write another value such as 0x12345678 or 0x00000000 to word 31, it reported the following errors， can you help to analyze this ? Thanks a lot!  

Hello!I have been trying to review and fix the configuration of my Ethernet LwIP+FreeRTOS STM32 project and I would like to ask more experienced people if I have correctly chosen memory locations, modified the linker script, configured MPU and a few other things. My project uses STM32F746VGT6 MCU that has 320KB of RAM and 1024KB of flash memory:MEMORY{ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K} Since this project uses Ethernet peripheral and LwIP library, a few memory sectors need to be defined: one for Tx Descriptor, one for Rx Descriptor, one for RX POOL and one for LwIP heap.I have set Tx and RX Descriptor addresses to 0x20048000 and 0x20048100 and checked in debugger that each one of them takes 160B of space, so 256B is more than enough to store a single Descriptor.I decided to store memp_memory_RX_POOL_base under 0x20040000 address in 32KB section. With ETH_RX_BUFFER_CNT defined to 16U, size of memp_memory_RX_P

My STM32F429 LWIP project stops all network comms after running for a few hours.  I am hoping that this is a known bug with a known fix. But I would appreciate any insight that anyone can provide.I have a CubeMX generated project using LWIP and FreeRTOS running on an STM32F429. I have an ethernet interface using a LAN8742A.After running for a few hours my project stops communicating and does not recover. I think I have ruled out any kind of memory or buffer exhaustion.  I suspect a race condition of some sort.Every time the comms stop, all of the RX descriptors are owned by the CPU and the ethernet RX descriptors are stuck in this same pattern.The numbers change but RxDescIdx is always (RxBuildDescIdx + 1).  And the counts are always = 1. heth->RxDescList->ItMode =          1    RxDescIdx    =          27    RxDescCnt =          1    RxDataLength =      118    RxBuildDescIdx =    26    RxBuildDescCnt =    1    pRxLastRxDesc    =      7734049    FreeRTOS is still running the idle

Hi All,I am using STM32U375RETx on in my project on a custom board. I am using 8 channels on ADC1 and 3 on ADC2. I want to scan all the channels using DMA. I have configured the ADCs in scan conversion mode using dma and have also configured the gpdma channels to connect with the ADCs.My issue is that I am unable to trigger a scan using software trigger. I am able to trigger a scan only once and then if I scan again, the adc callback is triggered. I verified my adc and gpdma logic by switching from software triggered dma scan to timer event triggered dma scan. This worked and the timer was able to always trigger the adc and update the callback to process the adc data. Could anyone please share what would be an example code for U3 to use software triggered adc dma. The github examples show only for timer trigger and not software trigger[link].Below is a cleaned up version of my main.c I appreciate any suggestions!Thanks!/* USER CODE BEGIN Header *//** ***********************************

Hello,I am experiencing what appears to be a BootROM or silicon issue on the STM32N657-DK.HardwareSTM32N657-DK Discovery board Boot from the on-board XSPI Flash External APSRAM connected to XSPI1Problem descriptionThe system works perfectly after a power-on reset.The FSBL starts correctly, the application runs, XSPI1 is initialized, and the APSRAM is fully functional. There are no communication errors with the memory.However, after XSPI1 has been initialized once, any subsequent reset causes the board to become completely unresponsive.The problem occurs with:pressing the NRST button, calling NVIC_SystemReset(), or resetting through the debugger.After such a reset:the CPU never reaches the FSBL, the debugger cannot stop in the reset handler, it appears that the BootROM itself never starts the boot process.The only way to recover the board is to completely remove the power supply and power it up again. A simple reset is never sufficient.Additional observationsIf XSPI1 is never initialize

Hi all, Experiencing yet another hurdle using the STM32N6: I am running into the issue where if I run the VENC as the JPEG encoder, where I previously found out how to properly run it in the first place, I get issues in the I2C slave communication…! Okay, what do I mean…i2c is configured as a slave. I receive/send all data via. DMA First stop for both directions of communication is the `HAL_I2C_AddrCallback` Maximum burst length of any i2c communication on my bus is 256 bytes The above mentioned limitation works very good and without issues, if I do not have the VENC running Problems arise, when I turn on the VENC, encoding each 2nd frame on PIPE1 that comes in through the DCMIPP. It is configured to convert one frame of ARGB24 into a JPEG. I used the middlewares from https://github.com/STMicroelectronics/STM32CubeN6/ and snippets from the VENC_JPEG_Encoding example (commit 8ab3b641, which is the latest as of writing). A list of some problems that I encounter, observed in parallel with

Hello, I am currently using SAI1A as Master and SAI2B as synchronous slave on the Nucleo F756ZG to send data to 2 DACs.One DAC is connected to SAI1A pins and the other is connected to SAI2B pins. The issue : SAI1A needs to be configured as master and SAI2B as its slave to be synchronized so the data are sent at the exact same moment to both DACs The second DAC is routed to the SAI2B SD, SCK, FS and MCLK pins but these are not used because the SAI2B is slave In this configuration, DAC 2 does not receive any signal from SAI2B SCK, FS and MCLK pins If both SAIs are configured as masters, there is a 20 microsecond latency between the data frames because the SAIs are not synchronized so there is a delay because of calling twice HAL_SAI_Trasmit_DMA function. I cannot afford this delay in my use case. Is there a way to clone or duplicate the SAI1A clock outputs to SAI2B pins so DAC 2 receives the clock signals as well, without modifying the routing ? Or reduce the delay to some nanoseconds wi

Dear ST Team,              I am currently porting an SBSFU/Trust Zone -based application from the STM32U585 to the STM32U5A5. The migration is almost complete, and the bootloader is functioning as expected.    The following operations complete successfully:BL2/SBSFU boots correctly. Image authentication and verification succeed. The application vector table is read correctly. The application jump is initiated using:boot_jump_to_next_image((uint32_t)&boot_jump_to_next_image, vt->reset);     Both addresses appear to be valid:MSP points to Secure SRAM. Reset vector points to Secure Flash with the Thumb bit set.The application successfully reaches the Reset_Handler, so the jump from SBSFU to the application appears to be successful.However, during the startup code, execution gets stuck while clearing the .bss section.The relevant startup code is shown below:ldr r2, =_sbssb   LoopFillZerobss FillZerobss:    movs r3, #0    str  r3, [r2], #4 LoopFillZerobss:    ldr r3, =_ebss    cmp r

Hello everyone,I am currently working on a project on Nucleo F756ZG where I need to :Use SAI1A and SAI2B to send audio data at the same time using TDM with 8 slots each SAI parameters are 128 bits data frames (so 16 bits per slot) Audio frequency 96k Master mode Use of HAL_SAI_Transmit_DMA to send the dataI managed to configure the SAIs, send and monitor the output data and it is working well but I noticed (an obvious I guess) latency between the payloads of the signals, between the 2 calls of the HAL_SAI_Transmit_DMA function, as you can see on the screenshot (12 us approximately). I would like to reduce this latency under 1 microsecond if possible. During my experimentations I noticed it was possible to set one SAI as master and the other one as its slave and only call HAL_SAI_Transmit_DMA once, but haven’t managed to make it work for now. Is it really possible ? I am looking for a code example to be sure to setup the SAIs properly. I can share more details of my code if necessary. T

I have read these forums and I see some have successfully got the F407 connected to KSZ8863 working. I am trying to do a simple non managed switch RMII PHY connection to the third port with no luck. I have confirmed the 50mhz clock input to the KSZ8863 is working as I can get port 1 and port 2 to transfer packets between each other, no issues at 100mbps just no packets to the processor. The schematic pdf I upload here shows my physical connections to the 407 and in the past I have successfully use the DP83848 out of the box. If anyone has a connection diagram to the 407 that works it would be much appreciated if you could share it along with any driver that you might have used.Update: I added a screenshot showing I do see rx data activity on the RII interface back at the processor.Thanks,

Can connect STM32H743 with LCD with MIPI interface ?

Hi all,I'm driving an NHD-1.5-128128G (SSD1351 controller, 4-wire SPI mode) from an STM32F303RE (Nucleo board) using the hardware SPI2 peripheral. The display has never lit up, and I've now run out of obvious things to check, so I'd appreciate a second pair of eyes.SetupDisplay: NHD-1.5-128128G Interface: 4-wire SPI (BS1=0, BS0=0, both tied to GND) MCU: STM32F303RE, HAL library, hardware SPI2 (not bit-banged) Pin mapping: CS, D/C, /RES driven as GPIO outputs; SCLK/SDIN via SPI2 hardware linesPower rails (all measured at the panel/FFC connector end, not just the breakout header)VCC: 13.0 V (measured on oscilloscope, confirmed at the connector) VCI: 3.3 V VDDIO: 3.3 V (measured directly at pin 4) VDD: not externally driven, only a 1 µF cap to GND per datasheet VCOMH / VSL: only connected to their respective decoupling caps per the reference schematic, no external driveWhat I've verified works correctly/RES toggles LOW→HIGH with correct timing (confirmed on scope) D/C toggles between comm

Hi all,Is there a replacement LCD/touch panel for STM32U5G9J-DK2. I found a company that sells them but they have a minimum order of 200. I’m only in need of the LCD/touch panel, I have the PCB (MB1860A). The manufacturer Rocktech show no info that I could find. Nothing comes up in octopart.com either.Thanks.

Hi, **Environment**- STM32F7xx LL Driver (STM32F7xx_HAL_Driver)- GCC arm-none-eabi 15.2 (also reproducible with GCC ≥ 12)- Compiler flag: `-fanalyzer`- File: `STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h`---**Problem**When building with `-fanalyzer`, GCC reports the following warning for several inline functions in stm32f7xx_ll_gpio.h:```warning: shift by count ('64') >= precision of type ('32')         [-Wanalyzer-shift-count-overflow]```**Root cause**`POSITION_VAL(VAL)` is defined as `__CLZ(__RBIT(VAL))`. When the analyzer considers `Pin = 0` as a possible runtime value (which it cannot rule out without additional constraints), then:- `__RBIT(0)` → `0`- `__CLZ(0)` → `32` (implementation-defined, GCC arm-none-eabi returns 32)- `32 * 2U` → `64` → shift of a `uint32_t` by 64 = **undefined behavior** per C11 §6.5.7The affected functions all follow the same pattern:// e.g. LL_GPIO_GetPinMode (line 307–311)return (uint32_t)(READ_BIT(GPIOx->MODER,    (GPIO_MODER_MODER0 << (POSIT