Timer cookbook wrong figure ?

[hdemi.1]

Shortly, cookbook says ETR frequency higher than core clock. It seems wrong. I am not sure if the information given is correct.

[waclawek.jan]

> cookbook says ETR frequency higher than core clock

I don't see it saying that. [EDIT] Okay now I see it in the narrative. However, the waveform on the figure don't match the text... [/EDIT] On that figure, APBx_CLK waveform, which is here the internal/core clock, is clearly higher frequency than ETR waveform.

JW

[waclawek.jan]

The narrative indicates, that the ETR prescaler is asynchronous. This means, that input signal on ETR may be higher frequency than the timer's internal clock, provided that the frequency after the asynchronous prescaler is lower than half the timer's internal clock.

JW

[Uwe Bonnes]

I suspect however that input pins are sampled with SYSCLK. Calrification from ST would be fine, what Inputs are not sampled and what the sampling clock is, if sampling applies.

[waclawek.jan]

Mention of asynchronous prescaler for ETR in the Cookbook is IMO not a mistake. Closer look at the diagrams indicate this, too:

 

Compare with the diagram for CHx:

 

The input clock to filter/synchronizer there is probably incorrect, as it ought to be selectable between DTS and CK_INT, see description of TIMx_CCMRx.ICxF.

Documentation can always be improved. IMO, RM should contain only the basic information, but should be augmented by a slew (dozens per IP) of application notes which drill down to the painful details. For example, in RMs, the timer chapters outght to be

• unified, i.e. only one (1) timer chapter per RM, dealing concisely with the differences between different variants of timers
• nomenclature of signals should be unified within and across RMs
• all features should be described in the narrative, in terms of functionality, accompanied by schematic and timing diagrams as appropriate; and not as an example
• the "PWM mode" and "one-pulse mode" definitively don't belong to RM, they are appnote stuff, RM may mention them as concrete application modes utilizing the related features
• carefully reviewed to purge copypaste relics, such as the 8-bit access mechanism of CCRx registers in the diagrams

And, of course, timers should be integral part of huge revamp of the interconnections, too.

Okay, enough of dreaming. ST does not care.

JW