STM32F767 : No Ethernet when APB2CLKDivider = RCC_HCLK_DIV8 or greater

Joerg Wagner · ‎2019-08-02

My SysClock is 200 MHz, AHB Prescaler=1.

I want to slow down some timer to filter glitches from external input.

But when APB2 peripheral clock is set lower than 50 MHz

the Ethernet DMA does not send any data: no ARP, UDP or TCP.

Even when ABP2 timer clock is set to 200 MHz to give it a try.

Why does APB2 peripheral clock takes advantage of Ethernet traffic?

I cannot find any dependencies on page 19 in the datasheet.

Thank you.

waclawek.jan · ‎2019-08-02

Cut down the program to ETH only. Still problem?

JW

Joerg Wagner · ‎2019-08-02

Yes, I wrote a tiny one without RTOS. I'm sure it has the same effect in one of the FW examples (udp_client).

You can reproduce it:

APB2 Peripheral clock >=50 MHz okay

APB2 Peripheral clock <50 MHz not okay

I didn't try other frequencies as well to find the border, i.e. using another SysClk freq to get 48 MHz.

Joerg Wagner · ‎2019-08-02

Okay, it does not depend on the absolute frequency.

It occurs when

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV8;

or greater.

DIV4 and less are okay.

waclawek.jan · ‎2019-08-02

So, now there's no APB2 peripheral used, i.e. if you read out RCC_APB2ENR it is all zero?

What's the read-out content of RCC_CFGR?

Do you use MII or RMII on ETH? Please read out and post content of SYSCFG_PMC.

How is the PHY clocked?

JW

Piranha · ‎2019-08-02

I tested this on NUCLEO-F767ZI at HCLK 216 MHz with Debug and Release builds of this code:

All APB2 suitable dividers (2, 4, 8 and 16) run perfectly fine and Ethernet performance isn't impacted also.

Conclusion... Nothing new, I'm telling it all the time - STM32 HAL ETH driver and lwIP implementation is broken beyond repair and nobody cares.

Joerg Wagner · ‎2019-08-02

RCC_APB2ENR = 0x0000940A (PPRE2=0x4, PPRE1=0x5, SWS1=1, SW1=1)

RCC_CFGR = 0x00004020 (USART6EN=1, SYSCFGEN=1)

Board is STM32F767-NUCLEO (STM32F767ZI), Firmware 1.15.0, CubeMX 5.2.1 generated project

PHY is clocked with 25MHz in Schematic.

Joerg Wagner · ‎2019-08-04

I tested this with the demo code of the 1.15.0 FW (LwIP_HHTP_Server_Netconn_RTOS):

Setting DIV8 in # line 253:

  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV8;

Ethernet does not work anymore.

Code is flashed, no Debug session.

The only APB2 peripheral Ethernet topic I found is in SYSCFG_PMC Bit 23: MII_RMII_SEL: Ethernet PHY interface selection

No other APB2 peripheral has a relationship with Ethernet.

@Piranha It's nice that your code works with any ratio. But I (and the others) have no advantage of this.

Probably you can share your experience as a library without providing the source code.

waclawek.jan · ‎2019-08-05

> Board is STM32F767-NUCLEO (STM32F767ZI),

OK so it's RMII with PHY having crystal and providing the reference clock.

Post content of SYSCFG_PMC.

JW

Joerg Wagner · ‎2019-08-05

SYSCFG_PMC = 0x800000

Bit 23 MII_RMII_SEL is set.

This means RMII is selected.