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I’m using SDIO + DMA on an STM32F407 and I need a “transfer complete” callback for SD writes/reads. What is the correct way to attach a user callback for SDIO + DMA completion when using the CubeMX‑generated SD/FATFS drivers?Thank you!

This is a bug with the code generation with STM32CubeMX2.In STM32CubeMX2, enable the middleware FreeRTOS, and in its settings Core → Main features → Advanced parameters selector → Task statistics and run-time, enable “Generate run time stats”.This generate a function in mx_freertos_app.c:/** * @brief Function to get the current value of the run-time timer counter. * @param None * @retval uint64_t The current counter value. */uint64_t GetRunTimeCounterValue (void){ return 0;}The return type is uint64_t, but it does not match the following type from FreeRTOSConfig.h (which cannot be changed in STM32CubeMX2): #define configRUN_TIME_COUNTER_TYPE uint32_t 

We are pleased to announce that version 6.18.0 of STM32CubeMX is now available. What is new in 6.18.0:  Added support for new microcontrollers in the STM32U3 series with 256 Kbytes and 512 Kbytes flash memory.  Added support for new microcontrollers in the STM32H5 series with 1 Mbyte flash memory.  Added support for new boards: NUCLEO-U345RC-Q, NUCLEO-U366RE-Q, STM32U366E-DK and            NUCLEO-H553ZG.  Added Start From Board feature for NUCLEO-U345RC-Q,  NUCLEO-U366REQ, NUCLEO-H553ZG,           NUCLEO-F446RE, NUCLEO-L432KC, and NUCLEO-L476RG.  Released the following new features:  Added support for PLAY for STM32H5 devices with 1 Mbyte of flash memory.  Add support for the MP25-DK board in the M33-TD flavor  Renamed all STM32CubeMX installers.  Added DMA comparison to the "Compare projects" feature.  Removed the JxBrowser dependency.  Upgraded the OpenSTLinux version to OpenSTLinux (OSTL) 6.2.1.  Main fixed issues in 6.18.0:   Refer to the STM32 microcontroller online documen

We are pleased to announce that version 6.18.0 of STM32CubeMX is now available.  What is new in 6.18.0:  Added support for new microcontrollers in the STM32U3 series with 256 Kbytes and 512 Kbytes flash memory.  Added support for new microcontrollers in the STM32H5 series with 1 Mbyte flash memory.  Added support for new boards: NUCLEO-U345RC-Q, NUCLEO-U366RE-Q, STM32U366E-DK and           NUCLEO-H553ZG.  Added Start From Board feature for NUCLEO-U345RC-Q,  NUCLEO-U366REQ, NUCLEO-H553ZG,           NUCLEO-F446RE, NUCLEO-L432KC, and NUCLEO-L476RG.  Released the following new features:  Added support for PLAY for STM32H5 devices with 1 Mbyte of flash memory.  Add support for the MP25-DK board in the M33-TD flavor  Renamed all STM32CubeMX installers.  Added DMA comparison to the "Compare projects" feature.  Removed the JxBrowser dependency.  Upgraded the OpenSTLinux version to OpenSTLinux (OSTL) 6.2.1.  Main fixed issues in 6.18.0:   Refer to the STM32 microcontroller online documen

Hi,Hardware: STEVAL-MKI109D (STM32H563ZI), ISM330DHCX on DIL24I'm developing custom bare-metal firmware for the STEVAL-MKI109D motherboard (STM32H563ZI), flashed via DFU, to communicate directly with an ISM330DHCX sensor on a STEVAL-MKI207V1 DIL24 adapter — not going through MEMS Studio.Problem:I can't get a valid SPI response from the sensor — WHO_AM_I consistently reads back as 0xFF. I've verified the following are correct against the ISM330DHCX datasheet:GPIO alternate function mapping (AF5, SPI1) confirmed via register dump SPI1 configuration matches Mode 3 (CPOL=1, CPHA=1), master mode, 8-bit frames, software NSS Read command format (0x80 | reg + dummy byte) and HAL_SPI_TransmitReceive sequence match the datasheet's read protocolThe sensor and DIL24 socket are confirmed good — sending the stock firmware's power-on/voltage-set commands over the same UART interface correctly reads WHO_AM_I = 0x6B.I'm currently using PA4/PA5/PA6/PA7 for SPI1 CS/SCK/MISO/MOSI in my firmware, but I sus

Dear all. I am currently planning to design a circuit without a DCDC, following the sequence VBat -> VDH -> VBP. To apply the L9908 to a 48V system, is it sufficient to set the voltage applied to the VBP pin from the DCDC to 36V or lower,as shown in Figure 91 of the datasheet?If so, what is the reason for using it in conjunction with a transistor like Tvbp1?Alternatively, what happens if only Tvbp1 is used without the DCDC?Since VDH and VBP each have monitoring functions, wouldn't there be no problem using them separately?  Thank you.

I'm exploring Secure Firmware Install of our product firmware, programming it to a Nucleo H563ZI development board straight out of the box, never previously used. I'm programming it with firmware binaries (including a bespoke OEM iRoT), option bytes and a couple of OBkeys files (one for certificate-based Debug Authentication, another for my iRoT’s keys). For these current experiments, I'm using a global license for installation.I'm using STM32CubeProgrammer and STM32 Trusted Package Creator version 2.22.0, with X-CUBE-RSSE package version 2.0.0 installed.Running the installation process within the GUI STM32CubeProgrammer, the following message boxes are displayed as it proceeds:* (Info) File download complete* (Info) MCU Reset* (Error) Error: Execution of RSS CMD failed, returned value = 0xFFEADE2A* (Error) Error: Failed to Process Area Number 1 of type HThe installation process stops after the last of these errors. After failure, the MCU's option bytes are in this state:OPTION BYTES B

Hi,I have this question because the reference manual states:“When flash high-cycle data area on Bank1 is enabled, the code memory map is not continuous from Bank1 to Bank2 on 2M- and 512K-byte devices.”So, does this mean that enabling high-cycle data sectors as EDATA on a 1MB device does not affect the code memory space, while on 2MB and 512KB devices, some sectors are reassigned for EDATA usage? If that’s the case, it seems like the 1MB device effectively has an extra 96KB of high-cycle data memory.Snaku

STM32H563MIY3Q is not available in LDO, is it available in Bypass mode ? Can an external LDO be used to power the core? Since there is no internal LDO inside the chip, is it unnecessary to keep the external Core voltage at 1.1 V before the VDD reach the POR threshold level? Do VDD and external core supply have timing sequence constraints? If an external LDO is used, can the VDDSMPS pin be connected to GND? Is there a reference schematic available? How should the software be configured when we use an external LDO for core power supply on this chip?

I'm planning to use an STM32G0 to make a Type-C to DP controller based on DP Alt Mode, and the high-speed data lines go straight to the DP links, but I'm not really sure how to connect them.Its shape would be something like this.According to the pin assignment of TA0356, item EThis is the Type-C socket definition I found from USB-IFThe mapping in TA0356 is shown in green font.The DPLinks connections are A2  -  A3 = TX1 → ML1B11-B10 = RX1 → ML0B2  -  B3 = TX2 → ML2A11-A10 = RX2 → ML3 Third, this is VESA's PDF,where PDPLinks correspond to shown in blue font.TX1→ ML0RX1→ ML1TX2→ ML2RX2→ ML3Because in the VESA PDF it shows a Type-C cable adapter, we need to swap the TX and RX internally. This is mentioned in the USBIF PDF.So, when the DPLinks in the VESA PDF switch to my design, the following changes will happen, shown in blue font.TX1→ ML1RX1→ ML0TX2→ ML3RX2→ ML2After converting like this, I got a sequence of different DPLinks than in TA0356, where ML0 and ML1 are the same, and ML2 and ML

Hi all,Ive been hand-populating prototype boards around an SPV1050 and for 2 out of 2 boards so far I’ve noticed the SPV1050 being defective right from the beginning. I then replaced the IC  via hot air rework and it worked flawlessly. That makes me wonder if my soldering setup kills the IC.Im using chipquik low temp soldering paste (the syringe is pretty empty, so it is far from fresh) and a Mini Heat plate with the default profile:80 sec rise to 150°C 80 sec rise to 170°C 60 sec rise to 230 90 sec keep at 230°C for soldering slow cooldownAre there any AN’s for this IC regarding soldering? I could nto find any info…Thank you for reading BRDamian 

Hello Team,I am facing RF read and write issues with the M24LR16E‑R EEPROM.The exact problem is as follows:When I take a new EEPROM and write data to it using an RF NFC reader for the first time, the operation is successful. However, during subsequent attempts to read and write: In some EEPROMs, RF read works but write fails but I2C read/Write working. In some devices, both read and write operations fail but I2C read/Write working. A few EEPROMs work correctly without any issues. In our application, we are using Sector 2 and Sector 3 for user data storage.When I read data from the problematic EEPROMs through St25 mobile application, I observe the following:Sector 0 and Sector 1 Security Status is 0x00. And the data read and write is working in these 2 sectors. Sector 2 to Sector 15 Security status: Current Security Status: 0x09 New Security Status: 0x09 Additionally, I receive the warning:“Sector locked. Security Status can only be changed through I2C.”I am not sure why the security

Hi Dear,I connected as picture my SWD pins. What is best solution for SWD Pins? Sould i capasitor, TVS or safety component? Is there any guide for STM32?     

I set PA6 and PA7 to ADC4_INx in CubeMX and ran CODE GENERATE.The generated main.c file implements MX_ADC4_Init(), but it doesn't seem to be called from anywhere.Should I call this somewhere in the main statement?Also, I tried implementing ADC reading within the main loop, but the return value of HAL_ADC_GetValue() is always 0 (even though it's actually around VDD/2).I've attached main.c. Could you please tell me the correct implementation method?

Hi everyone,I’d like to propose an enhancement for a future TouchGFX update.Currently, the clickable area of a ToggleButton is limited strictly to the dimensions of the button’s image. While this works in simple cases, it can be limiting in more practical UI designs.I suggest giving the ToggleButton a resizable clickable area, similar to the way the FlexButton works. Specifically, this would allow the developer to: Expand the clickable area independently via standard width and height properties. Freely position the toggle image within that area (just like an image placed inside a FlexButton). Use case example:Imagine a screen with multiple toggle options, each accompanied by explanatory text or an icon next to the button. With this feature, users could simply tap on the descriptive text or icon to activate the toggle, instead of having to precisely hit the small button image. This would significantly improve the user experience, especially on smaller screens or touch targets.I believ

 /* * Stl_Scheduler.c * * Created on: Jun 25, 2026 * Author: User */#include <stl_user_api.h>#include "stl_scheduler.h"#include "main.h"#include "app_threadx.h"#include "APP_Log.h"extern TIM_HandleTypeDef htim15;/* RAM & FLASH Tests definitions */#define FLASH_SECTION_SIZE 1024U#define RAM_SECTION_SIZE 128U#ifdef STL_DISABLE_RAM_BCKUP_BUF#define RAM_BACKUP_BUFFER_SIZE 0#else#define RAM_BACKUP_BUFFER_SIZE 32#endif// STM32H523#define TEST_RAM_START_ADDR (0x20000000U + RAM_BACKUP_BUFFER_SIZE)#define TEST_ROM_START_ADDR 0x08000000U//#define TEST_ROM_END_ADDR 0x0801A3FF//#define TEST_ROM_END_ADDR 0x0801A00FU#define TEST_ROM_END_ADDR 0x0801A3FFU//#define TEST_ROM_END_ADDR 0x0807F7FFU/*#if (defined (__GNUC__) && !defined (__CC_ARM) && !defined (__ARMCC_VERSION))extern void *_edata_load;#define TEST_ROM_END_ADDR ( (uint32_t)&_edata_load + 3)#endif*/// Runtime RAM test: 8 sections x 128 bytes = 1024 bytes#define TEST_RAM_SECTION_NB_RUN 8 /* only 8 RAM

Title: Bug Report: STM32G474 Vienna Rectifier firmware – TIM7 16-bit ARR register overflow (Wrong interrupt frequency)Hi everyone,I want to share my experience and a bug I recently discovered while working with the vienna_stm32G474 reference software (generated via ST eDesignSuite).🔍 The ProblemThe interrupt frequency for TIM7 was measured at 8734 Hz instead of the configured 2000 Hz.⚙️ Cause of the BugThe issue stems from the generic timer initialization function used across the project:cvoid DPC_MISC_ApplTimer_Init(TIM_HandleTypeDef AppTIM, uint32_t APPL_Freq_Desidered); This function assumes it is always dealing with 32-bit timers (like TIM2). However, TIM7 is a 16-bit basic timer.When calculating the Auto-Reload Register (ARR) value for the desired 2000 Hz frequency at a 170 MHz clock, the following math occurs:cTimers_ClockARR = (170000000 / 2000) - 1; // 85000 - 1 = 84999AppTIM.Init.Period = Timers_ClockARR; // Assigning 84999 to a 16-bit register Because TIM7->ARR is onl

Security:Introduction to STM32H5 security - stm32mcu “Approved version. Approved on: 10:25, 18 May 2026”The following links are broken:In the intro section, the text “For general STM32 security see this article and AN5156.”: The link “this article” is https://wiki.st.com/stm32mcu/wiki/Security:Security_overview which shows a “Page not found” error page. In section 2, in the bullet point about PCROP, the text “Obviously this feature is redundant with the availability of TrustZone® and HDP.”: The link “TrustZone” goes to Security:How to disable TrustZone in STM32L5xx devices during development phase - stm32mcu which is for a different MCU and not very relevant for STM32H5. In section 3, the text “For introduction on these features, refer to this guide.”: The link “this guide” is https://wiki.st.com/stm32mcu/index.php?title=Security:Guide_to_use_specific_security_feature&action=edit&redlink=1 - which does not exist. section 3.2, the text “For broader context follow here.”: The lin

 The following object detection models are not appearing on the STM32 Model ZooSSD_Mobilenet_V2(192x192)ST_YOLO_X_NANO(192x192)Have these models been removed or renamed?  

Is there any doco or app note on how to save/restore a STM32H7 CRC calculation (e.g. breaking up long CRC calculation into separate segments that requires re-initialization of CRC HW between segments)?

Dear Forum,I'm using a STM32F401 and implemented the I2C as Target transmitter (Slave) answering a I2C question. I'm programming the I2C CR2 (FREQ Bits) Register as follows with correct speed (42 MHz)I2C1->CR2 = ((DRV_RCC_GetPCLK1Freq() / 1000000u) & I2C_CR2_FREQ_Msk); I've noticed some spikes when the STM32 I2C controller generates the answer, see below (yellow markings)Blue: Clock generated by the controller (the clock speed is about 200kHz)Red: Adrdess Byte generated by the controller, Data Bytes generate by STM32 I2C transmitter (answer) with spikesWhen the FREQ Bits of I2C_CR2 Register are zero, this spikes doesn't occur, see belowThe Reference Manual RM0368 Rev 6 for the I2C CR2 writes:It is noticed that this FREQ bits must be configured to generate I2C compliant Signals. Anyhow from EMC perspective this spikes are bad because the radiate a wide spectrum. I've found nowhere information of correct I2C specifiation/behaviour of the Data Signal the be compliant

Thank you for taking the time to review my question.I migrated the Ux_Device_Audio_2.0_Standalone of STM32WBA6 to STM32H503 and successfully enumerated using USB FS. However, out of 1000 entries into the USBD_AUDIO_PlaybackStreamFrameDone function per second, half are 4 bytes long and half are 384 bytes (audio stream). I monitored the data using USBlyzer and did not see any upload data (EP IN) from STM32H503. I don't know where these 4 bytes come from, and this issue has been bothering me for several days.VOID USBD_AUDIO_PlaybackStreamFrameDone(UX_DEVICE_CLASS_AUDIO_STREAM *audio_play_stream, ULONG length){ /* USER CODE BEGIN USBD_AUDIO_PlaybackStreamFrameDone */ UCHAR *frame_buffer; ULONG frame_length; int32_t ret; UNUSED(ret); /* Get access to first audio input frame. */ ux_device_class_audio_read_frame_get(audio_play_stream, &frame_buffer, &frame_length); if (length) { HAL_GPIO_TogglePin(GPIOA, GPIO_PI

Hello, I have connected a sensor to my nucleo board to send data when sensor detects movement.I have introduced an ISR for that.void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){ if (GPIO_Pin == GPIO_PIN_0) { pirDetected = true; }} unfortunatelly with that approach everytime the sensor was triggered ( I was able to measure 3.3v on the OUT pin using voltmeter) my stm32 is kind a freezing.  I have introduced some testcode,extern "C" int main(void){ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); while (1) { if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_0)) { HAL_GPIO_Write

Hello,we have to use the STM32H573 in the 80 Pin WLCSP with temperature Range 3 (to 125°C). So STM32H573MIY3Q was chosen. Due to a mistake we didn't recognized that the internal LDO can't be used. Now we have no space for placing additional components as the inductor to use the SMPS. The STM is on a tiny board which is connected on a baseboard on this is more space for components.So now we have two options: Use an external LDO on the tiny board, we have 1,8V spare to burn down. How much current shall we consider (250 MHz). The maximum IDD ist stated with 125,2 mA, does any additional current has to be added?Use an external DCDC on the baseboard. In both cases the Questions are:How has the pins of SMPS to be configured (by hardware) to shut down the SMPS appropriately?Do we have to use the VCAP as an input?If STM staff is reading this please get in touch with us immediately. Thanks.So longMarwinEdits: Some minor spellings 

Board: NUCLEO-N657X0-Q (MB1940), STM32N657X0H (Cortex-M55 + Neural-ART NPU), Device ID 0x486 Rev Z.Toolchain: ST Edge AI Core v4.0.1-20581 (STM32Cube.AI 12.0.1-RC2), atonn 1.1.3-275, NetworkRuntime1201_CM55_GCC, arm-none-eabi-gcc 14.3.1 (STM32CubeCLT 1.21.0). SUMMARYA small int8 QDQ model (TCN: Conv2D x7 + Gemm x2, macc ~2.37M, int8 weights ~20 KB) generated with "stedgeai generate --target stm32n6 --st-neural-art" runs to completion on the NPU but produces wrong outputs: high-input forecasts collapse to baseline. Independent cross-check: onnxruntime on the same int8 ONNX gives 9.664 (ppm, log-domain output dequantized) on our golden window; the NPU returns ~0.26. Confirmed on hardware with ST's own "stedgeai validate --mode target" (regression head rmse 8.78, cos 0.589 vs the reference). LOCALIZED ON-TARGET TO A SINGLE OPPer-layer on-target validation (backbone stage outputs exposed as ONNX outputs):- input projection Conv: cos 0.999 (correct)- block 0 (dilated Conv + Slice + residual