About HansPLJ

HansPLJ · 2024-11-14

Hi!We are characterizing the ADC's in the STM32H7B3 µc. During temperature cycling of the HW we are observing some unexpected shifts in the conversion data from the ADC. The phenomena is observed across multiple HW units in varying degree. From one p...

HansPLJ · 2024-10-01

I have set up a project with the STM32H7B3 where I want the LPTIM1 to generate a synchronization signal that triggers a DMA driven SPI trancieve of 6*11 bits. The SPI is set up with wordsize 11. The DMA for both rx and tx is set up in circular mode w...

HansPLJ · 2024-04-18

Hi! I wonder if it is possible to set up the STM32H7B3 µC as a synchronous usart slave with the usart1 peripheral. From the reference manual it seems that it is only possible to set it up in 'SPI-mode'. The functionality I want is a USART slave that ...

HansPLJ · 2024-02-04

Hi!I am looking into the possibility on using LPTIM1 to trigger a DMA transfer with no CPU interrupt. This timer is chosen because it can be clocked directly by the HSE clock input. In the datasheet of STM32H7B3 (DS13139 - Rev 8) table 4, it states t...

HansPLJ · 2024-10-01

Yes. You are right, my SPI peripheral has only 8x8 bit fifo (4 half-words). However, when I try to use the HAL_SPI_Transmit_DMA instead of HAL_SPI_TransmitReceive_DMA, it works. I am able to send 6*11 bit words at the LPTIM1 sync event. Is there a di...

HansPLJ · 2024-04-29

Hi Omar!I don't see how this will solve the timing constraints since the state and phase of the clock will be unknown when enabling the CS. Maybe some additional logic and an analogue and-gate in front of the clock input could work.I will revisit thi...

HansPLJ · 2024-04-26

Hello Omar!Thank you for you input!I was a bit inaccurate in my post. My needs are maybe atypical, but I'm trying to implement an asynchronous communication protocol that communicates at a frequency determined by a continuous input clock. For the SPI...

HansPLJ · 2024-02-05

Thank you for the clarification!

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Shifts in conversion data from ADC on STM32H7B3

STM32H7B3 DMA handled SPI communication. Limitation to number of request per synch event?

STM32H7B3 synchronous usart slave with a continuous clock

DMA request generation on STM32H7

Re: STM32H7B3 DMA handled SPI communication. Limitation to number of request per synch event?

Re: STM32H7B3 synchronous usart slave with a continuous clock

Re: STM32H7B3 synchronous usart slave with a continuous clock

Re: DMA request generation on STM32H7