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STM32H7B3 synchronous usart slave with a continuous clock

HansPLJ
Associate II

Hi! 

I wonder if it is possible to set up the STM32H7B3 µC as a synchronous usart slave with the usart1 peripheral. From the reference manual it seems that it is only possible to set it up in 'SPI-mode'. The functionality I want is a USART slave that transmits data packets at a fixed rate(i.e. 1kHz) with no NSS, at the bit-rate determined by a continuous clock provided by the master. 

Any clarification would be appreciated! 

 

1 ACCEPTED SOLUTION

Accepted Solutions

Hello @HansPLJ 

 

Have you attempted to control the chip select using GPIO pins?

If your question is answered, please close this topic by clicking "Accept as Solution".

Thanks
Omar

View solution in original post

5 REPLIES 5
OSAKE.1
ST Employee

Hello @HansPLJ 

Synchronous slave mode is fully supported on USART1 of the STM32H7B3 MCU. For further details, please refer to Section 53.4 in the Reference Manual RM0455, as indicated in the table below.

OSAKE1_0-1714137847921.png

You can refer to this example which describes an USART-SPI communication (transmit/receive) between two boards where the USART is configured as a slave.

If your question is answered, please close this topic by clicking "Accept as Solution".

Thanks
Omar

Hello Omar!

Thank you for you input!

I was a bit inaccurate in my post. My needs are maybe atypical, but I'm trying to implement an asynchronous communication protocol that communicates at a frequency determined by a continuous input clock. For the SPI slave mode, there are timing requirements (time between chip select edge and first clock edge) that appear to not be compatible with my requirements of an continuous clock at the input.  

I suspect that this somewhat unusual functionality is not supported by st libraries. 

HP 

Pavel A.
Evangelist III

The baudrate detection function allows to precisely tune to the peer's rate.

 

Hello @HansPLJ 

 

Have you attempted to control the chip select using GPIO pins?

If your question is answered, please close this topic by clicking "Accept as Solution".

Thanks
Omar

Hi Omar!

I don't see how this will solve the timing constraints since the state and phase of the clock will be unknown when enabling the CS. Maybe some additional logic and an analogue and-gate in front of the clock input could work.

I will revisit this issue come summer. 

Thanks for your proposals

HP