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STM32H7B3 DMA handled SPI communication. Limitation to number of request per synch event?

HansPLJ
Associate II

I have set up a project with the STM32H7B3 where I want the LPTIM1 to generate a synchronization signal that triggers a DMA driven SPI trancieve of 6*11 bits. The SPI is set up with wordsize 11. The DMA for both rx and tx is set up in circular mode with half-word data alignment. DMA number of request is set to 6.  

In the process of getting it to work I started with only one request and it works. Increasing to 6 leads the DMA or the SPI to go into overrun. When reducing number of request to 4 it is working. 

Is there a limit to the number of request the DMA streams can handle?

The AHB1 is running at 200 MHz and the SPI clock frequncy is 20MHz. I have tried lowering the SPI clock with the same result. 

 

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