About ACohe.3

ACohe.3 · 2024-02-05

Hey,I use stm32h745, I want to use FDCAN1 communication with both cores.What is the effect of the decision on which core to perform initializer in the CubeMX?

ACohe.3 · 2024-01-24

Hey,I use STM32H745, I created ETH communication on the M4 core and it works well.Now I want ETH communication with two ports, one port per core.It is possible?In each core before the main while, I do:MX_LWIP_Init();/* create new tcp pcb */tcpb = tcp...

ACohe.3 · 2024-01-10

Hey,I use STM32H745ZI, I want to create an area for shared memory between the cores, I chose AXI SRAM because I need access as fast as possible for the M7 core.The shared memory is intended solely for shared information between the cores.I have two q...

ACohe.3 · 2024-01-07

Hey,I am developing a project in which the M7 core has CAN and USART communication which constantly communicates with components, the M4 core has Ethernet communication.I was interested in checking what the rate of the main loop is, so I defined two ...

ACohe.3 · 2024-01-04

Hey,I am starting to write a new project on STM32H745ZI.Core M7 is responsible for control and core M4 is responsible for communication with a computer.There is a lot of data that I want to share between the two cores, there is data that the access s...

ACohe.3 · 2024-01-25

In general, is it possible to configure two ports in an STM32 MCU?Have you seen an implementation of this before?

ACohe.3 · 2024-01-24

void PC_tcp_init(void) { /* create new tcp pcb */ tpcb = tcp_new(); err_t err; if (tpcb != NULL) { //err_t err; /* bind echo_pcb to IP and PORT (ECHO protocol) */ err = tcp_bind(tpcb, &ipaddr, SysIP.PORT); if (err == ERR_OK) {...

ACohe.3 · 2024-01-08

Thank you very much, you helped me!If I have a lot of use of sin cos tan in my code, is there a way to optimize the operations? Maybe a library that supports this or some setting?

ACohe.3 · 2024-01-04

Thank you very much, this information helps me!

ACohe.3 · 2024-01-04

First of all thanks for the answer.I looked at Figure 2 and also read section 2.2.1.According to Figure 2, it seems that SRAM1&2&3 are more accessible to Cortex-M4, AXI SRAM is more accessible to Cortex-M7 and SRAM4 is not adjacent to anyone, do I un...

User statistics

User Activity

Both cores with same communication

Dual port ethernet

STM32H745 - Shared memory definitions

STM32H745 Core Clock Rate

STM32H745 Dual Core SRAM

Re: Dual port ethernet

Re: Dual port ethernet

Re: STM32H745 Core Clock Rate

Re: STM32H745 Dual Core SRAM

Re: STM32H745 Dual Core SRAM