STM32H745 Dual Core SRAM

[ACohe.3]

Hey,
I am starting to write a new project on STM32H745ZI.
Core M7 is responsible for control and core M4 is responsible for communication with a computer.
There is a lot of data that I want to share between the two cores, there is data that the access speed is critical only for the M7 core and there is data that the access speed is critical for both cores.

my question:
Is there a connection between which part of SRAM I save the data and the data access speed for each core?
If so, where should I save data in different cases of needing access speed?

Thanks for the helpers!!

[FBL]

Hello @ACohe.3 

For data that needs to be accessed by both cores, it should be stored in a shared SRAM region, but the code should be optimized to minimize the number of accesses to this region. You can refer to Memory resource assignment in AN5557 and in Figure 2. STM32H7 dual‑core system architecture, for reduced memory access and switch between domains.

[ACohe.3]

First of all thanks for the answer.
I looked at Figure 2 and also read section 2.2.1.

According to Figure 2, it seems that SRAM1&2&3 are more accessible to Cortex-M4, AXI SRAM is more accessible to Cortex-M7 and SRAM4 is not adjacent to anyone, do I understand correctly?

In addition, according to section 2.2.1 only on SRAM3&4 it is written that part of the use is for shared memory between the two cores.

So if I want fast access for Cortex-M7 to the shared memory between the two cores, use AXI SRAM or SRAM4?

[SofLit · Accepted solution]

Hello @ACohe.3 ,

If you look at the AN4891 "STM32H72x, STM32H73x, and single-core STM32H74x/75x
system architecture and performance", using AXI-SRAM is a bit better in term of performance for CM7 than the other SRAMs located in D2/D3 domains. Don't forget there are bridges to connect D1 to D2/D3 domains.

[ACohe.3]

Thank you very much, this information helps me!