As per my knowledge, it is possible that controlling the Chip Select in software may result in some timing issues, especially when attempting to read the volatile Bank Status register.CS should be managed through software, as the synchronization betw...
Debugging dual-core in such cases is never that much easy. I guess, you need to make sure that M7 core initializes the M4 correctly. Then check the debugger setting for dual-core support.In some cases, the verification of SWD configurations for both...
