Can anyone comment on the prologue and epilogue of following CM7 code, particularly the content of r7 when the routine returns? {
0: b480 push {r7}
2: af00 add r7, sp, #0
if ((ANADIG_MISC->MISC_DIFPROG & ANADIG_MISC_MISC_DIFPRO...
Bored Saturday, I was just curious who's using which RTOS:FreeRTOS (Hideous Hungarian HorroRTOS, where code is fugly and deficiencies are touted as features ;)Azure/ThreadX (can't wait to see how Microsoft poisons this one ;)RTX (any actual CubeMX su...
Pavel, look closely at the OP. He edited the generated code. He then expected the change to appear in his .ioc.I'm still laughing (at the OP)... :face_with_tears_of_joy:
2) RX buffer cacheableThis is incomplete as explained in the OP and subsequent posts. Invalidate need to be done before the DMA to address line eviction and after the DMA completes to address speculative accesses. Further, the buffer should be alig...
