Hello,
Its just simple, when STM32_Programmer_CLI -c port=SWD mode=HotPlug -ob displ command is called - "Bit 21 DUALBANK: Dual-bank configuration" missing in report.
stdout:
-------------------------------------------------------------------
STM32CubeProgrammer v2.18.0
-------------------------------------------------------------------
ST-LINK SN :
ST-LINK FW : V3J15M7B5S1
Board : STLINK-V3SET
Voltage : 3.27V
SWD freq : 8000 KHz
Connect mode: Hot Plug
Reset mode : Software reset
Device ID : 0x482
Revision ID : Rev W
Device name : STM32U575/STM32U585
Flash size : 2 MBytes
Device type : MCU
Device CPU : Cortex-M33
BL Version : 0x93
Debug in Low Power mode enabled
UPLOADING OPTION BYTES DATA ...
Bank : 0x00
Address : 0x40022040
Size : 48 Bytes
0%
100%
OPTION BYTES BANK: 0
Read Out Protection:
RDP : 0xAA (Level 0, no protection)
BOR Level:
BOR_LEV : 0x0 (BOR Level 0, reset level threshold is around 1.7 V)
User Configuration:
TZEN : 0x0 (Global TrustZone security disabled)
nRST_STOP : 0x1 (No reset generated when entering Stop mode)
nRST_STDBY : 0x1 (No reset generated when entering Standby mode)
nRST_SHDW : 0x1 (No reset generated when entering the Shutdown mode)
SRAM134_RST : 0x1 (SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs)
IWDG_SW : 0x1 (Software independent watchdog)
IWDG_STOP : 0x1 (IWDG counter active in stop mode)
IWDG_STDBY : 0x1 (IWDG counter active in standby mode)
WWDG_SW : 0x1 (Software window watchdog)
SWAP_BANK : 0x0 (Bank 1 and bank 2 address are not swapped)
BKPRAM_ECC : 0x1 (Backup RAM ECC check disabled)
SRAM3_ECC : 0x1 (SRAM3 ECC check disabled)
SRAM2_ECC : 0x1 (SRAM2 ECC check disabled)
SRAM2_RST : 0x1 (SRAM2 is not erased when a system reset occurs)
nSWBOOT0 : 0x1 (BOOT0 taken from PH3/BOOT0 pin)
nBOOT0 : 0x1 (nBOOT0 = 1)
PA15_PUPEN : 0x1 (USB power delivery dead-battery disabled/ TDI pull-up activated)
IO_VDD_HSLV : 0x0 (High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V))
IO_VDDIO2_HSLV: 0x0 (High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V))
Boot Configuration:
NSBOOTADD0 : 0x100000 (0x8000000)
NSBOOTADD1 : 0x17F200 (0xBF90000)
Write Protection 1:
WRP1A_PSTRT : 0x7F (0x80FE000)
WRP1A_PEND : 0x0 (0x8000000)
UNLOCK_1A : 0x1 (WRP1A start and end pages unlocked)
WRP1B_PSTRT : 0x7F (0x80FE000)
WRP1B_PEND : 0x0 (0x8000000)
UNLOCK_1B : 0x1 (WRP1B start and end pages unlocked)
Write Protection 2:
WRP2A_PSTRT : 0x7F (0x81FE000)
WRP2A_PEND : 0x0 (0x8100000)
UNLOCK_2A : 0x1 (WRP2A start and end pages unlocked)
WRP2B_PSTRT : 0x7F (0x81FE000)
WRP2B_PEND : 0x0 (0x8100000)
UNLOCK_2B : 0x1 (WRP2B start and end pages unlocked)
