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IPCC interrupt issue in stm32mp157A ?

Srikanth1
Associate III

Hello,

We are using STM32MP157A.

We are working on IPCC from A7-0,A7-1 to M4.

We are getting IPCC interrupt A7-1 to M4,But when we are not getting interrupt from A7-0 to M4.

In cubeMx it is showing NVIC to IPCC RX1 and TX1, but not showing to RX0,TX0.

we are using CubeMX 6.3.0 and firmware version is STM32Cube_FW_MP1_V1.4.0.

0693W00000Y8qf8QAB.pngBut in reference manual showing IPCC_RX0,IPCC_TX0 these interrupts are available.

0693W00000Y8qfSQAR.png 

in our application we need interrupts both A7_0 ,A7_1 processors to M4 controller.

please help us in this regards.

regards

srikanth

1 ACCEPTED SOLUTION

Accepted Solutions
PatrickF
ST Employee

Hi,

there should be no issue, IPCC if full duplex and provide one interrupt channel from A7 to M4 and one interrupt channel to M4 to A7.

  • IPCC RX1 and TX1 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-M4 side
  • IPCC RX0 and TX0 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-A7 side

See https://wiki.st.com/stm32mpu/wiki/IPCC_internal_peripheral#Overview

For Linux kernel, the interrupt management could be done by either processor #0 or #1, but only one processor at a time (I'm not Linux SW expert). This behavior is likely managed by relevant GIC interrupt routing settings during Linux run time.

I guess Linux kernel will then distribute maibox events to relevant SW tasks.

Although from GIC HW point of view you can enable IPCC RX0 and TX0 interrupts to both A7#0 and A7#1, that's generally not a good idea as there could be interrupt management SW timing courses on both CPUs which might need semaphore management which will impact interrupt latency.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

1 REPLY 1
PatrickF
ST Employee

Hi,

there should be no issue, IPCC if full duplex and provide one interrupt channel from A7 to M4 and one interrupt channel to M4 to A7.

  • IPCC RX1 and TX1 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-M4 side
  • IPCC RX0 and TX0 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-A7 side

See https://wiki.st.com/stm32mpu/wiki/IPCC_internal_peripheral#Overview

For Linux kernel, the interrupt management could be done by either processor #0 or #1, but only one processor at a time (I'm not Linux SW expert). This behavior is likely managed by relevant GIC interrupt routing settings during Linux run time.

I guess Linux kernel will then distribute maibox events to relevant SW tasks.

Although from GIC HW point of view you can enable IPCC RX0 and TX0 interrupts to both A7#0 and A7#1, that's generally not a good idea as there could be interrupt management SW timing courses on both CPUs which might need semaphore management which will impact interrupt latency.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.