Hi @dkal
Using DDR with HSI as root clock is not possible (even if path exist to PLLs) because HSI is not stable enough (frequency an jitter) to fit USB and DDR JEDEC requirements.
Regards
Hi @dkal
if you are writing to DDR, maybe double check the correct DM Vs DQ/DQS wirings on your schematics. We had seen similar behavior when customers swapped Data Mask and Bytes which mean x32-bits write works but not bytes.
Regards.
Hi @Srikanth1
those has already been answered in https://community.st.com/t5/stm32-mpus-products/usb-phy-issue-in-stm32mp157a/m-p/616874/highlight/true#M10576
USBPHYC_MONITOR definition could be found in RM0475 (same PHY in STM32MP13)
NO other missi...
HI @macrobert
Please have a look to this page:
https://wiki.st.com/stm32mpu/wiki/Interrupt_overview
My understanding is that you cannot manage interrupt in user space, you need to have a driver going thru irqchip
https://wiki.st.com/stm32mpu/wiki/Ov...
Hi,
This missing register should be present in a future revision of the STM32MP15 reference manual.Meanwhile, you could find it in the STM32MP13 reference manual (RM0475) which uses same USBPHYC.
There is some missing IP identification registers whic...
