Hi,
regarding DDR, did you read following application notes ?
AN5168 How to configure DDR on STM32MP1 MPUs
AN5692 DDR memory routing guidelines for STM32MP13x product lines
Did your PCB routing follows one of the provided example and/or have corr...
Hi,
I guess the issue might not be linked to DDR timing settings. Could you elaborate more on the
Does this mean the 8-bit write is ok in some situations ?
When it fail, what is the read value ? 0 ? value from another write ? Maybe worth to fill a l...
Hi,
I think DDR tests are done using only 32-bits access and/or with cache enabled (as goal is to check timings, not wiring), which might mean only 32-bits access are done to the DDR (i.e. no byte mask differentiation).
We have already seen this kind...
Hi @jhi
this post might help you
https://community.st.com/t5/stm32-mpus-products/change-default-tf-a-and-u-boot-serial-linux-console/m-p/195035/highlight/true#M5683
Regards.