Moved from STM32H7B0 DFSDM Synchronization: Abnormal Clock Output During Register Configuration to a new thread in STM32CubeMX forum.
Thank you for your detailed instructions!
I set a breakpoint as you suggested and found that the audio clock is indeed generated as you said, but its behavior is abnormal, and not modified by codes after.
Unfortunately, I cannot measure the waveform of the audio clock (DFSDM1 ACLK) directly, as it is not mapped to any IO output by default.
To debug this, I re-mapped the DFSDM1 clock output (DFSDM1_CKOUT) from PC2_C to PB0. Surprisingly, the clock waveform on PB0 is now output correctly at the expected frequency (2.4MHz).
This suggests a potential issue with the original GPIO pin PC2_C. Could this be due to accidental ESD damage to PC2_C?
I would greatly appreciate your insights on whether this pin re-mapping approach is feasible for long-term use, or if there are better ways to diagnose/recover the original pin functionality.
It appears there is a discrepancy in the CubeMX UI labeling when configuring DFSDM filter synchronization for the STM32H7B0. Specifically, the UI incorrectly refers to "Synchronous with DFSDM0" instead of "Synchronous with Filter0".
This mislabeling likely stems from architectural differences between STM32 families: In devices like the STM32F413, which support multiple DFSDM peripherals, synchronization between peripherals is a valid configuration.
This UI mislabeling may confuse users into incorrectly associating synchronization with a non-existent "DFSDM0" instead of the actual master filter (Filter0), leading to configuration errors or unnecessary troubleshooting.
Could you confirm if this is a known UI issue in CubeMX for the STM32H7 series?If so, will there be a fix in future CubeMX versions to correct the labeling to "Synchronous with Filter0"?
appended is my ioc
