2021-10-02 06:48 AM
I am selecting the pins PD4, PD5, PD6, and PD7 in the '.ioc' file.
The .ioc when only my nor pins are selected.
The pins only when ethernet is being enabled.
When I enable both the ethernet and the external nor flash.
I see the overlapping of pins when I enable both ethernet and the external nor flash.
Will this would be a problem for failing my functions. If so what should I do to get it done?
Thanks.
Could you please help me with this.!
2021-10-02 09:16 AM
Cube / .IOC files, doesn't sound like my thing at all..
Parallel NOR Flash? That's going to use a huge number of pins, people have migrated to QSPI NOR Flash
The F429 should be able to separate pin usage between peripherals (ETH, FMC), unlike the F1 which could get internally conflicted.
The F4 can only do ONE function per pin, what's going to prevail is the last one set in.
The pin choices for ETH are likely for be relatively limited, as are the Address/Data busing of the FMC.
Sounds like you have got a conflict, or expectation on the ETH side that it can use a specific pin/functionality.
Probably want to unpack the actual pin level configuration code generated, and look at the data sheet, around ALL the pins you've involved.