I am trying to sample a 2MHZ sine wave signal at 5.1MHZ adc setting using DMA. But the output of the signal look distorted. ADC clock : 72MHZ I am using stm32f303rE

[waclawek.jan]

To me looks reasonable. Your input signal clips at negative, and the "wobble" you see is the effect of limited number of samples per source period.

JW

[Patukes]

If the source signal frequency(100kHz) is low , the ADC sample then look fine.

[waclawek.jan]

Try to sample it at the same sampling frequency ratio, i.e. 100kHz / 2MHz * 5.1Msps = 255ksps.

JW

[Patukes]

There is no change, it is till distorted

[waclawek.jan]

What is still distorted? 100kHz signal sampled with 255ksps?

That's my point, you can't see a "nice" sine if you interpolate only a few points (in your case 2.55 in average) per period.

JW

[Patukes]

@Community member​ 

Thank you, I understand , I have interpolated it and got the proper sine wave. I would rather want to implement dual interleaved mode ADC. Please do you have a sample code for stm32F303RE

[waclawek.jan]

No, sorry.

JW