If from the "Clock Configuration" tab Fadc > 36Mhz then the Clock prescaler for the ADC is automatically set to /2 where the /1 is diabled. For > 72MHz it is /4 where /1 and /2 are disabled. Rev. 2 has an additional /2 divider that has been taken into account in the HAL code but not in CubeMX I assume.
Code snippet from stm32h7xx_hal_adc.c:
/**
* @brief Configure boost mode of selected ADC.
* @note Prerequisite condition to use this function: ADC conversions must be
* stopped.
* @param hadc ADC handle
* @retval None.
*/
void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
else /* STM32H7 silicon Rev.V */
{
freq /= 2U; /* divider by 2 for Rev.V */
if (freq <= 6250000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
}
else if(freq <= 12500000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
}
else if(freq <= 25000000UL)
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
}
else /* if(freq > 25000000UL) */
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
}
#endif /* ADC_VER_V5_3 */
}
