NVIC ISERx registers address are wrong in STM32F446RE

[PK]

I am using STM32F446RE. I am using the STM32CubeIDE. As STM32F446RE is Cortex-M4 based processor I have also gone through the M4 generic user guide and found that the range of NVIC_ISER0- NVIC_ISER7 is 0xE000E100- 0xE000E11C. But when I ran the code in debug mode and go to the NVIC registers I see the below addresses.

Can I resolve this issue or is it hardware issue?

Can anyone help please

[Piranha]

Registers are described in SVD files. The one in your picture seems to be wrong. Probably you can try replacing it from there:

https://www.st.com/en/microcontrollers-microprocessors/stm32f446re.html#cad-resources

[PK]

@Piranha​ Thanks for your response.

Now the address got changed but still not matching with the  M4 generic user guide ( NVIC_ISER0- NVIC_ISER7 --> 0xE000E100- 0xE000E11C)

[TDK]

The SVD file from the link provided by Piranha doesn't even have ISER3-7 registers, and the values for ISER0-2 are correct. Are you sure you replaced the correct file?

It's a text file. You can open it and verify the values in the SVD are correct.

    <peripheral>
      <name>NVIC</name>
      <description>Nested Vectored Interrupt
      Controller</description>
      <groupName>NVIC</groupName>
      <baseAddress>0xE000E100</baseAddress>
...
      <registers>
        <register>
          <name>ISER0</name>
          <displayName>ISER0</displayName>
          <description>Interrupt Set-Enable Register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SETENA</name>
              <description>SETENA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ISER1</name>
          <displayName>ISER1</displayName>
          <description>Interrupt Set-Enable Register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SETENA</name>
              <description>SETENA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>ISER2</name>
          <displayName>ISER2</displayName>
          <description>Interrupt Set-Enable Register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SETENA</name>
              <description>SETENA</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
            </field>
          </fields>
        </register>

[PK]

Yeah I copied correct file only. I checked the SVD file. Only ISER0, ISER1 and ISER2 are there. Others are not there. I also tried adding them manually. Still I see the same issue.

 

ISER0 -> 0xE000E100 .this is correct

but ISER1-4 are not correct here.

ISER1-> 0xE000E004

ISER2-> 0xE000E008

ISER3-> 0xE000E00C

ISER4-> 0xE000E010

Those should be 0xE000E104, 0xE000E108, 0xE000E10C and 0xE000E110 respectively

[TDK]

I don't know why the IDE would be displaying registers that don't exist in the SVD file, or why the locations don't match.

[mattias norlander]

Hi @PK​,

Thanks for bringing to attention. I think there may be multiple issues here.

The NVIC register is described both in the CORE svd-file and the device specific svd-file.

To explain: The SFR-view loads two svd-files. One for the core itself and one for the specific STM32 product describing its peripherals. See below each top-node represents an svd-file:

I think you checked the NVIC node inside the STM32F446 parent? Check inside the Cortex_M4 instead.

I think it is a bug if the device specific file contains NVIC node as well. But I have to check internally. The same files are delivered for CubeIDE that are used for IAR and Keil. And if IAR/Keil dont load two svd-files, then I can understand if there is a need for information duplication. I am no expert on those external tools, but will check...

Will also ask svd-file team to check if the ISERx registers are on the correct addresses regardless of which svd-file. Looks like there may be issues in this aspect as well.

[mattias norlander]

Had some discussions with the responsible team.

1. They will prioritize to check the correctness of the core svd-files so that there is a way to see the registers correctly.
2. Regarding the issue that the device specific files also contains core nodes like NVIC... ST provides more than 120 svd-files for the different STM32 devices. Reviewing all of them to remove NVIC and other "core-related" nodes from the device specific files, that only should be part of the core svd-file, is a huge undertaking. It will be done step-by-step with much lower prio since relying on the core svd-file and this node in the SFR-view should work today (assuming no issues found in first point above :-])

That said, if you spot issues with svd-files for STM32 peripherals, then we try to fix these with high attention. So keep the bug reports coming. Thanks!

[e.oztoklu]

I am having the same issue also, I am not able to change this address value. is there properly a working file for svd .

ST needs to check this issue.. or if anyone else can explain to us how to change this SVD file to suit the NVIC address which those are exist in generic user guide pdf

[PK]

Hi @e.oztoklu​ ,

I got some temporary solution. Instead of checking the NVIC register in Cortex_M4 check into the microcontroller specific NVIC section. There the addresses are correct.

Ex. In my case:

I see the below addresses which are correct. but here all the registers are not available