STM32MP151C memory size that Coprocessor(Cortex-M4) can use

[HMasu.1]

I want to know the memory size of STM32MP151CAA3 that Coprocessor(Cortex-M4) can use.

https://wiki.st.com/stm32mpu/wiki/Boot_chains_overview#STM32MP15_boot_chain

this wiki page says that coprocessor(Cortex-M4) program loaded in MCUSRAM(384kB).

Does this means that the maximum size of "program and using data" of Coprocessor(Cortex-M4) program is up to 384kB?

In this case, If I want to run a program with a size larger than 384kB on coprocessor(Cortex-M4), is there workaround such as using external memory?

Best regards.

H. Masuda

[Olivier GALLIEN]

Hi @HMasu.1​ 

You can also add the 64kB of the RETRAM to reach 448kB.

For solution using external memory let me come back to you after some further confirmation.

Else maybe you can think about offloading some part on A7 ?

This AN is providing some interesting rules and guidelines :

https://www.st.com/resource/en/application_note/dm00560967-migrating-from-stm32f469479-line-to-stm32mp151-stm32mp153-and-stm32mp157-lines-stmicroelectronics.pdf

Olivier

[Olivier GALLIEN]

Hi @HMasu.1​ ,

I got confirmation of fact that there is no sustainable solution of external flash for code execution from M4.

Performances are too poor and highly impact real time.

FMC and QSPI flash or RAM can be eventually used to store some data ( DMA access) .

So recommended solution is really to think if your application can be better split between A7 and M4 to stick in 448kB M4 side.

Hope it help,

Olivier

[HMasu.1]

Hi @Community member​ 

Thank you for your valuable information.

I will consider what you have taught me.

Let me ask you some additional questions.

Q1) Is it impossible to load a part of the Cortex-M4 program to DDR and execute the program on DDR?

Q2) Is it possible to access DDR from the Cortex-M4 program?

Q2 assumes the following behavior.

1) To communicate between Cortex-A7 and Cortex-M4, I create the shared memory area on DDR.

2) The Cortex-A7 program stores the data in the shared memory area on DDR and notify Cortex-M4 program that have stored data by RPMsg.

3) The Cortex-M4 program get data on DDR

Best regards.

H. Masuda​

[Olivier GALLIEN · Accepted solution]

Hi @HMasu.1​ 

Q1)  Cortex-M4 is not intended to access DDR content. Cortex-M4 has no cache and asynchronous path to AXI bus has not been optimized for that, so Cortex-M4 performance will be very largely impacted.

Furthermore, accessing small chunk of data to a DDR is never a good choice, as this will affect the DDRCTRL scheduling and so the performance of other AXI masters accessing the DDR SDRAM.

Although it is possible from HW point of view, in our Linux deliveries, Cortex-M4 access is forbidden inside TrustZone address space controller for DDR (TZC).

Q2) Data exchange between A7 and M4 using DDR is possible.

We deliver an complete exemple of this here :

https://wiki.st.com/stm32mpu-ecosystem-v1/wiki/How_to_exchange_large_data_buffers_with_the_coprocessor_-_principle

Hope it help

Olivier

[HMasu.1]

Hi @Community member​ ,

Thank you for your answer.

I understood that Cortex-M4 program can not be loaded to DDR.

Please let me ask you one more question.

Can I locate work area or data area of Cortex-M4 program to DDR? (It is not shared area between Cortex-M4 and Cortex-A7)

For example, is it impossible that I locate global variables of Cortex-M4 program to DDR and locate Cortex-M4 program to SRAM?​

Best regards.

H. Masuda​