how to activate level 2 cache for stm32mp157 ?

Roman Andronov · ‎2024-01-29

PatrickF · ‎2024-01-29

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

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PatrickF · ‎2024-01-29

Hi @Roman Andronov

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.