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STM32MP1 ldrex/strex support between A7 and M4 cores.

Jan Humpl
Associate II

Hi,
I'm searching any information about how exclusive access (LDREX / STREX instructions) is implemented in STM32MP157 silicon. Unfortunately, it seems that ST assumes that this information is obvious.

Based on ARM documentation, the synchronization is either provided by the SCU or the memory shall be marked Shareable (see https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/use-in-multi-core-systems).

Based on the STM32MP157 datasheet, figure 1: the SCU unit is part of the Level-2 cache connected to the dual-A7. However, the M4 core is on another bus. So I suppose that the SCU will not ensure A7 <-> M4 exclusive access.

The other option is Sharable memory. So the question is: is functionality of ldrex/strex instructions between A7 and M4 cores guaranteed when the memory is marked as Shareable in MMU / MPU?

Based on another articles, the behavior of Sharable memory depends on implementation of bus, bus interconnection and other devices on the bus (in this case the "devices" are A7 and M4 cores). I have searched through the entire reference manual, but I did not find any information regarding this issue.

May be this is obvious and I missed some well know information. You may think that HSEM is always a better solution, but I will have to disagree. 
Thank you in advance for any useful information.

1 REPLY 1

The reasonable inference is that there effectiveness doesn't extend beyond the A7 itself.

So things that function autonomously, like peripherals, other cores, aren't the source of random deadlocks.

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