STM32MP151 IBIS model DDR issue

[MBG]

Hello,

I am following AN4803 to simulate my board with an STM32MP151 with DDR3L memory, but there seems to be a problem with the IBIS model. 

These IBIS models have missing receiver voltage thresholds, which may affect analysis:
IBIS File: C:\Users\...\IBIS\stm32mp151_153xaa_lfbga448_sm.ibs
IBIS Model: MSD_D3RP3L_48
Model does not have a [Receiver Thresholds] section.
Only Vinh and Vinl thresholds are specified in the [Model Spec] section, and will be used for both AC and DC thresholds.
Net: $9I75\DDR_DQ0
Controller pin: U1.E21 (DDR_DQ0)
Net: $9I75\DDR_DQ1
Controller pin: U1.F21 (DDR_DQ1)
Net: $9I75\DDR_DQ2
Controller pin: U1.H21 (DDR_DQ2)
Net: $9I75\DDR_DQ3
Controller pin: U1.E20 (DDR_DQ3)
Net: $9I75\DDR_DQ4
Controller pin: U1.J21 (DDR_DQ4)
Net: $9I75\DDR_DQ5
Controller pin: U1.H20 (DDR_DQ5)
Net: $9I75\DDR_DQ6
Controller pin: U1.H22 (DDR_DQ6)
Net: $9I75\DDR_DQ7
Controller pin: U1.G19 (DDR_DQ7)
Net: $9I75\DDR_DQ8
Controller pin: U1.N22 (DDR_DQ8)
Net: $9I75\DDR_DQ9
Controller pin: U1.R21 (DDR_DQ9)
Net: $9I75\DDR_DQ10
Controller pin: U1.P21 (DDR_DQ10)
Net: $9I75\DDR_DQ11
Controller pin: U1.T20 (DDR_DQ11)
Net: $9I75\DDR_DQ12
Controller pin: U1.V20 (DDR_DQ12)
Net: $9I75\DDR_DQ13
Controller pin: U1.R20 (DDR_DQ13)
Net: $9I75\DDR_DQ14
Controller pin: U1.U21 (DDR_DQ14)
Net: $9I75\DDR_DQ15
Controller pin: U1.V21 (DDR_DQ15)
IBIS Model: MSD_D3RP3L_ODT60
Model does not have a [Receiver Thresholds] section.
Missing Vinh and Vinl thresholds in the [Model Spec] section.
Only Vinh and Vinl thresholds are specified in the [Model] section, and will be used for both AC and DC thresholds.
Net: $9I75\DDR_DQ0
Controller pin: U1.E21 (DDR_DQ0)
Net: $9I75\DDR_DQ1
Controller pin: U1.F21 (DDR_DQ1)
Net: $9I75\DDR_DQ2
Controller pin: U1.H21 (DDR_DQ2)
Net: $9I75\DDR_DQ3
Controller pin: U1.E20 (DDR_DQ3)
Net: $9I75\DDR_DQ4
Controller pin: U1.J21 (DDR_DQ4)
Net: $9I75\DDR_DQ5
Controller pin: U1.H20 (DDR_DQ5)
Net: $9I75\DDR_DQ6
Controller pin: U1.H22 (DDR_DQ6)
Net: $9I75\DDR_DQ7
Controller pin: U1.G19 (DDR_DQ7)
Net: $9I75\DDR_DQ8
Controller pin: U1.N22 (DDR_DQ8)
Net: $9I75\DDR_DQ9
Controller pin: U1.R21 (DDR_DQ9)
Net: $9I75\DDR_DQ10
Controller pin: U1.P21 (DDR_DQ10)
Net: $9I75\DDR_DQ11
Controller pin: U1.T20 (DDR_DQ11)
Net: $9I75\DDR_DQ12
Controller pin: U1.V20 (DDR_DQ12)
Net: $9I75\DDR_DQ13
Controller pin: U1.R20 (DDR_DQ13)
Net: $9I75\DDR_DQ14
Controller pin: U1.U21 (DDR_DQ14)
Net: $9I75\DDR_DQ15
Controller pin: U1.V21 (DDR_DQ15)

[PatrickF]

Hi  

I'm not expert, but I see you are using MSD_D3RP3L_48, which as per AN4803 is an output driver model (i.e. writing data to DDR3L, when ODT is disabled on STM32MP1 side). Sound logical not to have receiver parameters.

For data receiver (i.e. reading data from DDR3L, when ODT is enabled in STM32MP1 side), you should use the MSD_D3RP3L_ODTyy with yy the ODT level you have (60 shown in AN4803, 80 seems recommended in AN5168).

Maybe this is the cause of the error you get.

Regards.

[MBG]

Hi Patrick,

Thank you for your quick reply.

So you think that Hyperlynx reporting an error with receiver thresholds on MSD_D3RP3L_48 can be ignored since it is a driver model? That makes sense to me. 

However I still don't understand the error with IBIS Model: MSD_D3RP3L_ODT60 (2nd half of my error log), which is the one you suggested I should use when the STM32 is a receiver.

[FredL · Accepted solution]

hi,

Please apply the modifications attached in the txt files.
1- add the description of the diff pin
2- add receiver thresholds for MSD_D3RP3L_48
3- change model type of MSD_D3RP3L_ODT60 in I/O
4- add receiver thresholds for MSD_D3RP3L_ODT60

Rgs