STM32MP135 ST PMIC Driver panic

[efancier]

We designed a STM32MP135 based SOM, without using the ST I2C PMIC,  I was able to disable the PMIC driver in TF-A by removing the i2c 4 node in TF-A's dts file, while I could not get the same result for optee-os,  even I removed the i2c-4 node in optee-os' dts file, I still got message saying panic, following is the full log:

NOTICE: CPU: STM32MP135D Rev.Y
NOTICE: Model: STMicroelectronics STM32MP135F-DK Discovery Board
WARNING: VDD unknown
INFO: Reset reason (0x4):
INFO: Pad Reset from NRST
INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000
INFO: FCONF: Reading firmware configuration information for: stm32mp_io
INFO: Using SDMMC
INFO: Instance 1
INFO: Boot used partition fsbl1
NOTICE: BL2: v2.6-stm32mp1-r2.0(debug):2021.05-5963-ga40218f3c9(a40218f3)
NOTICE: BL2: Built : 09:55:01, Jul 5 2023
INFO: BL2: Doing platform setup
INFO: RAM: DDR3-1066 bin F 1x4Gb 533MHz v1.53
INFO: Memory size = 0x20000000 (512 MB)
INFO: BL2: Loading image id 1
INFO: Loading image id=1 at address 0x30006000
INFO: Image id=1 loaded: 0x30006000 - 0x30006246
INFO: FCONF: Reading FW_CONFIG firmware configuration file from: 0x30006000
INFO: FCONF: Reading firmware configuration information for: mce_config
INFO: FCONF: Reading firmware configuration information for: dyn_cfg
INFO: FCONF: Reading firmware configuration information for: stm32mp1_firewall
INFO: BL2: Loading image id 4
INFO: Loading image id=4 at address 0xde200000
INFO: Image id=4 loaded: 0xde200000 - 0xde20001c
INFO: OPTEE ep=0xde200000
INFO: OPTEE header info:
INFO: magic=0x4554504f
INFO: version=0x2
INFO: arch=0x0
INFO: flags=0x0
INFO: nb_images=0x1
INFO: BL2: Loading image id 8
INFO: Loading image id=8 at address 0xde200000
INFO: Image id=8 loaded: 0xde200000 - 0xde27e250
INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0xc0400000
INFO: Image id=2 loaded: 0xc0400000 - 0xc040f750
INFO: BL2: Skip loading image id 16
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0xc0000000
INFO: Image id=5 loaded: 0xc0000000 - 0xc00e4444
NOTICE: BL2: Booting BL32
INFO: Entry point address = 0xde200000
INFO: SPSR = 0x1d3
E/TC:0 0 Panic at core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c:218 <initialize_pmic_i2c>
E/TC:0 0 TEE load address @ 0xde200000
E/TC:0 0 Call stack:
E/TC:0 0 0xde203f19
E/TC:0 0 0xde21da13
E/TC:0 0 0xde20910f
E/TC:0 0 0xde21c4b3
E/TC:0 0 0xde21c57d
E/TC:0 0 0xde21cd03
E/TC:0 0 0xde21e6f9
E/TC:0 0 0xde203dff
E/TC:0 0 0xde200198

Any one have suggestion on this?

[Erwan SZYMANSKI]

@efancier , @lebeer ,
I will check with OPTEE expert tomorrow, but from what I can see for now, it seems that the panic generated by OPTEE is caused inside its probe function without passing into config conditions. When I look at the device tree from @lebeer (I do not know if you have both the same) it seems that stpmic1 compatible is still present inside the dts. For me it is so logical that this function is called, but I precise that I am not an OPTEE expert, so this is just a first look at the issue.

I will come tomorrow with more information.

@efancier , can you provide your current device tree too to analyze it internally ? As well as your OPTEE config file if you can.

Kind regards,
Erwan.

[efancier]

@Erwan SZYMANSKI, Thank you for looking at this.  The device tree and config file are attached here.

[Erwan SZYMANSKI]

Hello @efancier ,
First can you please remove the "accepted answer" on my previous message as I think it does not correct your issues ? :)

Secondly, looking at your config file, could your remove your CFG_STPMIC1=y as you will not need it if you are in power discrete, without use of PMIC ? It could be a root cause of your issue.

Kind regards,
Erwan.

[efancier]

@Erwan SZYMANSKI ,  Thank you for your reply.  I clicked on accepted answer button accidently.  it has been removed.   The CFG_STPMIC1=y should be over written  to CFG_STPMIC1=n by my build system,  but I will double check.

[Erwan SZYMANSKI]

@efancier ,
Thanks, please double check and let me know :)

Kind regards,
Erwan.

[Vince60]

Hi @Erwan SZYMANSKI ,

I have same issue with STPMIC1DPQR and OPTEE. Console log on UART4 is:

I/TC: Non-secure external DT found
I/TC: Embedded DTB found
I/TC: OP-TEE version: 3.16.0-dev (gcc version 11.3.0 (GCC)) #5 Fri 28 Jan 2022 02:28:18 PM UTC arm
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: WARNING: All debug access are allowed
E/TC:0 0 Panic at core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c:218 <initialize_pmic_i2c>
E/TC:0 0 TEE load address @ 0xde200000
E/TC:0 0 Call stack:
E/TC:0 0  0xde203cb5
E/TC:0 0  0xde21bc31
E/TC:0 0  0xde208cc5
E/TC:0 0  0xde21a817
E/TC:0 0  0xde21a8e1
E/TC:0 0  0xde21afd7
E/TC:0 0  0xde21c7f9
E/TC:0 0  0xde203af7
E/TC:0 0  0xde200198

Do you have any info about possible solution?

Thanks

Vincent

[debugging]

CFG_STPMIC1?=y  in conf.mk solved the panic for me. (also discrete board) (was using a clean developer tree( it seem the conf.ml defaults to PMIC?=y because ST DK/EV boards use PMIC) This fix should be the accepted answer.

[Vince60]

Hi @debugging ,

Thanks for your help but error is still here.

In optee-os/stm32mp135f-my_board.dts file, reconfiguration of I2C4 is done as on TF-A (this part is successfully loaded) but in stm32_i2c.C function

bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr,
             unsigned int trials, unsigned int timeout_ms)

error is displayed when OPTEE is loaded.

Do you have any idea to solve this problem?

Thanks

[arifbalik]

I have the same issue. This seems to be pretty common one as I found many posts on this. I have the PB7 and PE15 as my I2C, TFA boots correctly but OPTEE panics 

[Vince60]

Hi,

Problem solved by using I2C4 in secured world in OPTEE.

Hope this will solve your problem.

Regards