2020-12-21 07:58 AM
2020-12-22 03:23 AM
Semiconductors normally have no hard but soft limits. Expect some lower figure of merits like higher current surge, less max TX porer and less RX sensivity. Hard limits may be imposed by internal logic. Maybe with normal frequency settings, the range for the PLL may not allow to set below 150 MHz. That you could perhaps be worked around by using a slight lower base frequency oscillator that would shift that limit.