I've spent some time recently trying to prototype a small project based on the STM32H503 which would need to have the ADC and DAC running simultaneously with multiple channels of analog I/O via DMA. I was able to get this all coded up but discovered that sometimes on reset the DAC outputs were not as expected. Cycling power or asserting NRST would sometimes fail and sometimes operate properly. A quick look through the H503 errata revealed that this is a known issue - "2.2.21 Invalid DAC output voltage for several DAC kernel clocks".
The problem is that the DAC requires both a bus clock and a kernel clock, and likely because of a synchronization issue between them the kernel clock and bus clock must be the same. Ordinarily this wouldn't be a huge problem except that the DAC and ADC share their kernel clock and the ADC is limited to a maximum 125MHz for its kernel clock. This results in the derived requirement that the AHB bus clock cannot exceed 125MHz when both the DAC and ADC are used together, which seriously limits the overall bandwidth of the entire STM32H503 MCU.
I attempted a few approaches to mitigate this by running the DAC and ADC from PLL2 with an output of 125MHz which still running the AHB at 250MHz but sensing the condition where the DAC outputs were not tracking properly. When the condition was detected I would rapidly disable and re-enable PLL2 to alter its phasing - this almost works and in many cases was able to establish proper operation of the DAC, but I found it wasn't sufficiently reliable and it could take many attempts to achieve proper sync.
In the end I've given up and will use external converters for my application. It's disappointing that the H503 was so close to meeting my requirements but this errata made it not quite right.
