2020-03-02 03:26 AM
I decided to have a go at producing a VGA display with the STM32L4.
640x480 @ 60Hz is the lowest resolution compatible with most displays (and VGA to HDMI convertors - many TVs only have HDMI ports these days). This resolution requires a pixel clock of 25.175MHz, which is usually derived from a crystal.
But you can get close to this frequency using the PLL. Set the MSI to 24MHz, the input divider to 5 (/M) and the multiplier to 21 - this produces a VCO frequency of 100.8MHz, which divides down to 50.4MHz (for the System clock) and 25.2MHz (for SPI/Pixel clock).
25.2MHz is only 0.1% off from 25.175, which should work (haven't quite finished off the rest of the software yet.....).
2020-03-02 04:34 AM
A few random remarks:
JW
2020-04-16 02:57 AM
This article might interest you. It seems difficult to get stable timing but it is possible.
2020-04-22 01:53 AM
Thanks for the article Nikita91. I did try my method of generating a 25.2Mhz using the MSI and found that it didn't look too bad on a small monitor, but when I put it up on a large TV it was very wobbly - it turned out to be a great way of visualising clock jitter (..the expression "don't count your chickens before they hatch" comes to mind).
My original aim for using 640x480 @60Hz was to minimise RAM and processor usage on a STM32L chip. Thankfully the 640x480 @ 72Hz (31.5MHz pixel clock) is just as easy to produce - but you need to use a 4MHz (or 8MHz/16MHz) crystal (4MHz x 63=> 252MHz, /4=>63MHz, /2=>31.5MHz). This resulted in a rock solid display - but I still need to fine tune the Hblank/Vblank timings (when I get the time to revisit it). To ensure unvarying timing and minimise interrupt overhead, I DMA the whole screen in one block (rather than using a line by line DMA) - it does mean you lose some extra memory for the horizontal blanked areas.