Hello
I'm always confused with the ADC clock config of H7 devices. ok, H7 is not a device for noob but ever after spending days reading datasheets, users manual, appnote, and filling spreadsheets, when starting cube MX, you will always find that the clock scheme you want to use is not available (and the one you think not reachable, is available).
I'm using the H757, BGA240+40 @ VOS1. ADC2 and ADC3 configured to sample 6 channels each in scan mode. No injected channel.
According to my understanding (please correct me where I'm wrong) :
ADC1,2 are on D2 domain, AHB1 bus
ADC3 is on D3 domain, AHB4 bus
ADC max clock = 50MHz (after all prescalers)
When using the async clock from RCC, max adc_ker_ck = 160MHz
When using sync clock,
- adc_hclk is the AHB1 (ADC1,2) or AHB4 (ADC3) clock : max 200MHz. This is the clock source for the digital part only.
- adc_sclk is sys_ck when HPRE = 0 (1:1 ratio), sys_ck/2 otherwise (1:2 or more ratio). This is the clock source for ADC SAR converter (limited to 50MHz AFTER the prescalers)
When playing with the clock divider in cube MX, I can see that the ADC sync clock prescaler (1:1 1:2 1:4) are not always available). My guess was : The software allow only prescalers that make the clock <=50MHz). Right ? Let's see...
In this example, adc_sclk = sys_ck (HPRE = 0), so 200MHz.
The only sync prescaler allowable should be 1:4.
Or, for ADC1,2 1:2 is also available. For ADC3, all are available.
I've just upgraded the software to the latest version. Previous one is another story (not sure, I guess ADC3 sync mode was just not available at all).
It would be nice if ST indicates :
- What is the max adc_hclk clock
- What is the max adc_sclk clock
- Confirm if cubemx is in the wrong or not
- For the next release, integrate the ADC clock config in the clock section, to be sure about what we are configuring and what is the real ADC clock selected.
Thanks for your help !
