Write access to PSRAM on XSPI in memory mapped mode

[williams-one]

Hello,

I have a question regarding write access to a PSRAM connected via XSPI in memory mapped mode on a STM32H7RS.

I do not completely understand if having the PSRAM memory mapped makes it available to the ECU as if it is internal RAM, meaning that it can be used to perform read and write operation of any size.

Reading some docs (e.g. the reference manual), it seems that every aspect of PSRAM management in memory mapped mode is handled automatically by the MCU configuring parameters like the CSBOUND chip select bound.

But looking at the code samples (such as this one https://github.com/STMicroelectronics/STM32CubeH7RS/blob/d06484d3e19c7d6fc963bbec5d754637f237c1ed/Projects/STM32H7S78-DK/Examples/XSPI/XSPI_PSRAM_MemoryMapped/Boot/Src/main.c#L200), it looks that the user must take into consideration aspects like page crossing and write time as indicated by the comment

     /* In memory-mapped mode, not possible to check if the memory is ready
    after the programming. So a delay corresponding to max page programming
    time is added */

By the way CSBOUND is not configured in the example code.

Can you help me better understand which is the proper way to manage an external PSRAM and its limitation.  Also, is using a RAM connected via FMC any different?

[KDJEM.1 · Accepted solution]

Hello @williams-one,

The aim of the purpose of adding this delay is: If you configure XSPI to operate with memories using command mode. There is an internal register in PSRAM that indicates if the memory is ready for other commands or no (BUSY: operate in process, READY: no operations in process and ready for taking orders).

-> It is recommended to enter auto-polling mode after every operation.

In the other side, after memory mapped activation, we have not a way to confirm that any operation is done, so the delay is used like a "safety" to ensure that the operation is done.

So, this delay is not a fundamental step to make the operation do, but it is added to ensure the operation's "safety".

About the CSBOUND, thank you for bringing this issue to our attention, I reported it internally for checking. 

The main features of the FMC are the following:
• Interface with static-memory mapped devices including:
– static random-access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (4 memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data

An example of how to configure the FMC to interface an STM32 MCU with an external memory: How to configure the FMC peripheral to interface an STM32 MCU with an external NOR flash memory 

I recommend you to look to RM0477 section 23.7 NOR flash/PSRAM controller.

Internal ticket number: 200908 (This is an internal tracking number and is not accessible or usable by customers).

Thank you.

Kaouthar

[williams-one]

Thanks @KDJEM.1 for the additional info.  They were really helpful!