STM32U585 MPU cacheability?

[BDoon.1]

I am using an STM32U585QI.  I have some memory mapped PSRAM that I'm using.  I have enabled DCACHE, but do I have to manually do something with the MPU for it to cache memory accesses to/from the memory?  The reference manual says:

"In addition, the AHB bus traffic to the memory regions can be cacheable or noncacheable.
An incoming memory request to DCACHE is defined as cacheable according to its AHB
transaction memory lookup attribute.

...

These AHB attributes depend on the memory protection unit (MPU) programming for the
addressed region."

If I don't call HAL_MPU_Enable or set it in any way, will memory mapped and DMA reads/writes to the external memory region go through the data cache?

[mƎALLEm · Accepted solution]

Hello,

According to the RM0456 / Figure 120:

The PSRAM memory region is at 0x6XXX XXXX.

And according to the PM0264  "STM32 Cortex®-M33 MCUs and MPUs programming manual"/ Table 19:

That region attribute is by default cacheable: Write-Back\Write-Allocate (WBWA). So normally no need to configure the MPU to set it cacheable.

Hope that answers your question.